
HW 86010
Integration Manual
© Höft & Wessel AG
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Subject to amendment, errors excepted
IM86010-1-22_.doc
1.22
30.07.04
AM
page 29/46
3.4.6.6
Precautions to avoid reset problems
The host hardware must assure an appropriate environment that avoids
unwanted resets. The reset behaviour is a main source of integration
problems and requires specific attention.
Please make sure that the following conditions are fulfilled during operation:
V3P3 must not drop below 2,7V. This will trigger a low voltage reset.
At power-up of the HW 86010 the RSTBI signal should be either high
impedance (not connected) or logic HIGH. A logic LOW during power-up
may be interpreted as external reset and may result in unwanted mode
selection.
If the host hardware is not able to assure the appropriate RSTBI level
during power-up, it may use a short reset afterwards to emulate a power-up
reset.
DSRO and CTSO are outputs of the HW 86010. The host hardware must
never actively drive these signals for any other purpose than entering the
download mode.
The external reset is triggered by the falling edge of the RSTBI signal. Make
sure that the fall time (90% down to 10% of V3P3) is less than 50ns.
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