Design Guide
Revision 1.12
1998-08-12
HMS F
IELDBUS
S
YSTEMS
AB
Page 8 (35)
2.1.1 Parallel Interface
The parallel interface is based on a 1kB dual ported memory (DPRAM). From the users point of view the
DATATRANSFER modules have the same function as a normal RAM memory, containing all input data
and output data transferred over the fieldbus. Applications using this interface will get the best
performance of the ANYBUS module.
To prevent data loss and that incorrect data is read from the memory due to collisions, access to the data
stored in the DPRAM is controlled in a protocol.
Only the parallel interface is described in this design guide. See chapter 4 for detailed information
2.1.2 Serial Interface
Some applications can not access the dual port RAM via address and data bus, but have a free serial link.
Therefore it is possible to operate through the serial interface. The initialisation procedure will be held in a
similar way to the Dual Port RAM solution.
The serial interface is available as an asynchronous interface, RS232 with TTL level..
The asynchronous serial interface allows the ANYBUS DATATRANSFER module to exchange data
asynchronous with external microprocessors. It has a standard non-return to zero (NRZ) format (one start,
eight data, one stop and none parity bit). Several baud rates up to 38.400 bit/s are available.
Design Guide Asynchronous serial interface document: ABDT-DGA-10
DPRAM
RAM
FLASH
LED´ s
Reset
circuit
MICRO
CONTROLLER
A
pp
li
ca
tion Interface
1kx8
Data Bus
XTAL
EXTAL
Serial Interface
WD
RESET
D[0..7]
A[0..18]
Address Bus
FIELDBUS
INTERFACE
Oscillator
TxD
RxD
Figure 2. AnyBus DT block schematics
