Design Guide
Revision 1.12
1998-08-12
HMS F
IELDBUS
S
YSTEMS
AB
Page 28 (35)
7.2 Signal Description
Note: pull-up resistors mentioned in this chapter are recommended to be 100 k
Ω
.
Pin 1,2
Power supply to bus interface
+5V power supply to bus interface. This must be a isolated power supply, for example powered by a
DC/DC converter.
Pin 3,4
Not connected.
Isolation distance.
Pin 5,6
Power supply to Electronics.
+5V power supply to module electronics.
Pin 7,8
Serial interface signals.
Transmit and receive signals for asynchronous serial interface. The RX signal has to be pulled-up via a
resistor on the application side.
Pin 9 - 18
Address bus.
Address bus to DPRAM. The A
NY
B
US
modules are normally equipped with a 55 ns or faster DPRAM.
A
0
is LSB and A
9
is MSB.
Pin 19 - 26
Data bus.
Data bus to DPRAM. The A
NY
B
US
modules are normally equipped with a 55 ns or faster DPRAM. D
0
is LSB and D
7
is MSB.
Pin 27
/BUSY
IIndicates simultaneously access of the same memory location from both sides of the DPRAM. Active
low signal. Open collector output. This signal has to be pulled-up via a resistor on the application side.
When using the handshaking system the BUSY signal does not have to be implemented. If the
application side shall access the Dual Port Memory regardless of the bus update cycle, it is necessary to
use the BUSY signal to ensure that there will be no simultaneous read/write on the same byte from
both sides of the DPM.
Pin 28
/IRQ
DPRAM interrupt signal. Indicates when new data is available in the Dual Port Ram. The AB-DT
control register shows who has access to the DPRAM.
This signal is an active low open collector output. This signal shall be pulled-up via a resistor on the
application side.
Pin 29
/RD
DPRAM Read signal. From application to DPRAM. Active low.
Pin 30
/WR
DPRAM Write signal. From application to DPRAM. Active low.
