58
6.3.2 RTC Status Register (RTCSR)
Address: 0x001, Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0.5secF
1secF
ARF
0
R
R
R
R
R/W
R/W
R/W
R
(1) ARF
ARF bit
Setting
0
The setting of each alarm register with the AR bit set is not the same as
that of each counter register. (Initial value)
1
The setting of each alarm register with the AR bit set is identical to that
of each counter register. At this time, an interrupt occurs if the ARI bit
is set to “1.”
[Clear condition]
This counter is cleared when “0” is written with the ARF bit set to “1.”
(2) 1secF
1secF bit
Setting
0
A second has not elapsed yet. (Initial value)
1
A second has elapsed.
[Clear condition]
This counter is cleared when “0” is written with the 1secF bit set to
“1. ”
(3) 0.5secF
0.5secF bit
Setting
0
A half second has not elapsed yet. (Initial value)
1
A half second has elapsed.
[Clear condition]
This counter is cleared with zeros when “0” is written with the 0.5secF
bit set to “1.”