11
0
7.
Eeternal Interrupt
7.1
SH7760 External Interrupts
Figure 7.1 shows a mechanism for the SH7760 interrupt signal.
Table 7.1 shows the levels for respective interrupt signals.
As shown in Figure 7.1, interrupt signals from devices within Solution Engine2 are converted into the /IRL signals
by FPG, then output to the /IRL [3:0] of the SH7760.
Figure 7.1 InterruptSignal Mechanism
Table 7.1 Interrupt Levels for Interrpt Signals
No
Interrupt request source
Interrupt input pin
Interrupt signal level
Remarks
1
PCMCIA controller (SIRQ3)
/IRL[3:0]
/IRL[3:0]=0001
Interrupt level 14
2
PCMCIA controller (SIRQ2)
/IRL[3:0]
/IRL[3:0]=0101
Interrupt level 10
3
PCMCIA controller (SIRQ1)
/IRL[3:0]
/IRL[3:0]=1000
Interrupt level 7
4
PCMCIA controller (SIRQ0)
/IRL[3:0]
/IRL[3:0]=1010
Interrupt level 5
5
UART controller chA
/IRL[3:0]
/IRL[3:0]=0110
Interrupt level 9
6
UART controller chB
/IRL[3:0]
/IRL[3:0]=0011
Interrupt level 12
7
H8/3048F-ONE
/IRL[3:0]
/IRL[3:0]=0010
Interrupt level 13
8
Extension slot (IRQ3#)
/IRL[3:0]
/IRL[3:0]=0000
Interrupt level 15
9
Extension slot (IRQ2#)
/IRL[3:0]
/IRL[3:0]=0100
Interrupt level 11
10
Extension slot (IRQ1#)
/IRL[3:0]
/IRL[3:0]=0111
Interrupt level 8
11
Extension slot (IRQ0#)
/IRL[3:0]
/IRL[3:0]=1001
Interrupt level 6
PCMCIA controller
MR-SHPC-01 V2T
/SIRQ3
/SIRQ2
/SIRQ1
/SIRQ0
FPGA
SH7760
/IRL3
/IRL2
/IRL1
/IRL0
Power supply controller
H8/3048F-ONE
/H8_IRQ(PB3)
TxD ,RxD
UART
(ST16C2550)
INTA TXA ,RXA
TXB ,RXB
INTB
CN1
Host
IRQ -> IRL
conversion
Extension slot
IRQ2#
IRQ1#
IRQ0#
IRQ3#
local bus