Hitachi Global Storage Technologies
7.9.7 Device Terminating Write DMA ..................................................................................53
7.9.8 Host Terminating Write DMA......................................................................................54
7.10 Drive address setting............................................................................................................55
7.11 Addressing of HDD registers...............................................................................................56
8.0 General........................................................................................................................................59
8.1 Introduction............................................................................................................................59
8.2 Terminology...........................................................................................................................59
9.0 Deviations from standard..........................................................................................................61
10.0 Register .....................................................................................................................................63
10.1 Alternate Status Register .....................................................................................................64
10.2 Command Register ..............................................................................................................64
10.3 Data Register........................................................................................................................64
10.4 Device Control Register......................................................................................................65
10.5 Drive Address Register ........................................................................................................65
10.6 Device/Head Register .........................................................................................................66
10.7 Error Register.......................................................................................................................66
10.8 Features Register..................................................................................................................67
10.9 LBA High Register ..............................................................................................................67
10.10 LBA Mid Register .............................................................................................................67
10.11 Sector Count Register ........................................................................................................67
10.12 Status Register ...................................................................................................................67
11.0 General......................................................................................................................................69
11.1 Reset response......................................................................................................................69
11.2 Register initialization ...........................................................................................................70
11.3 Diagnostic and Reset considerations ...................................................................................71
11.4 Power-off considerations .....................................................................................................72
11.4.1 Load/Unload ...............................................................................................................72
11.4.2 Emergency unload ......................................................................................................72
11.4.3 Required power-off sequence .....................................................................................72
11.5 Sector Addressing Mode......................................................................................................73
11.5.1 Logical CHS addressing mode ...................................................................................73
11.5.2 LBA addressing mode ................................................................................................73
11.6 Power management features ................................................................................................74
11.6.1 Power mode ................................................................................................................74
11.6.2 Power management commands ..................................................................................74
11.6.3 Standby/Sleep command completion time .................................................................74
11.6.4 Standby timer ..............................................................................................................75
11.6.5 Status...........................................................................................................................75
11.6.6 Interface capability for power modes .........................................................................75
11.6.7 Initial Power Mode at Power On ................................................................................75
11.7 Advanced Power Management (ABLE-3) feature...............................................................75
11.7.1 Performance Idle Mode ..............................................................................................76
11.7.2 Active Idle Mode ........................................................................................................76
11.7.3 Low Power Idle Mode ................................................................................................76
11.7.4 Transition time ............................................................................................................76
11.8 S.M.A.R.T. Function ...........................................................................................................77
Содержание IC25N020ATMR04
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