Hitachi HD6433822, Руководство по оборудованию

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Table 15-3 Control Signal Timing (cont)
V
CC
= 1.8 V to 5.5 V, AV
CC
= 1.8 V to 5.5 V, V
SS
= AV
SS
= 0.0 V, T
a
= –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable
Values
Reference
Item Symbol Pins Min Typ Max Unit Test Condition Figure
External clock high t
CPH
OSC
1
70 — — ns V
CC
= 4.5 V to 5.5 V Figure 15-1
width
100 — — V
CC
= 3.0 V to 5.5 V *
2
140 — — V
CC
= 2.6 V to 5.5 V
200 — — V
CC
= 2.2 V to 5.5 V Figure 15-1
400 — — Except the above
X
1
— 15.26 — µs
or
13.02
External clock low t
CPL
OSC
1
70 — — ns V
CC
= 4.5 V to 5.5 V Figure 15-1
width
100 — — V
CC
= 3.0 V to 5.5 V *
2
140 — — V
CC
= 2.6 V to 5.5 V
200 — — V
CC
= 2.2 V to 5.5 V Figure 15-1
400 — — Except the above
X
1
— 15.26 — µs
or
13.02
External clock rise t
CPr
OSC
1
— — 20 ns V
CC
= 4.5 V to 5.5 V Figure 15-1
time
— — 30 V
CC
= 2.6 V to 5.5 V *
2
— — 55 Except the above Figure 15-1
X
1
— — 55.0 ns
External clock fall t
CPf
OSC
1
— — 20 ns V
CC
= 4.5 V to 5.5 V Figure 15-1
time
— — 30 V
CC
= 2.6 V to 5.5 V *
2
— — 55 Except the above Figure 15-1
X
1
— — 55.0 ns
Pin
RES
low width t
REL
RES
10 — — t
cyc
Figure 15-2
Input pin high width t
IH
IRQ
0
to
IRQ
4
, 2 — — t
cyc
Figure 15-3
WKP
0
to
WKP
7
t
subcyc
ADTRG
,
TMIC
TMIF, TMIG,
AEVL, AEVH
Input pin low width t
IL
IRQ
0
to
IRQ
4
, 2 — — t
cyc
Figure 15-3
WKP
0
to
WKP
7
, t
subcyc
ADTRG
,
TMIC,
TMIF, TMIG,
AEVL, AEVH
UD pin minimum t
UDH
UD 4 — — t
cyc
Figure 15-4
modulation width t
UDL
t
subcyc
Notes:
1.
Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2.
Internal power supply step-down circuit not used
370