hilscher COMX 100CA-DN, Руководство по конструкции

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Design-In - Electrical Aspects 56/78
COMX Communication Modules | Design Guide
DOC100901DG18EN | Revision 18 | English | 2013-12 | Released | Public
© Hilscher, 2002-2013
The following table gives the values for the timing parameters for COMX 10 modules using the
netX 10 chip, for COMX 50 modules using the netX 50 chip, for COMX 51 modules using the netX
51 chip and for COMX 100 using the netX 100 chip. For exchangeability of COMX 10, COMX 50,
COMX 51 and COMX 100 communication modules use the values of column
Common of Table
37.
Symbol Description COMX 10
netX 10 COMX 50
netX 50 COMX 100
netX 100 COMX 51
netX 51 Com-
mon
t
1
t
AS min.
Minimum address setup time 0 ns 1.9 ns 0 ns 0 ns 2 ns
t
2
t
BV max.
Maximum Time from cycle start
until BUSYn signal is valid 5.7 ns 35.5 ns 30 ns 5,7 ns 40 ns
t
BAR typ.
Typical BUSY active time (read ac-
cess)
See note 2
- 50 ns 80 ns - - t
3
t
BAR max.
Maximum BUSY active time (read
access)
See important note 1
68 ns - - 68 ns -
t
BAW min.
Minimum BUSY active time (write
access) 0 ns 0 ns 0 ns 0 ns 0 ns t
4
t
BAW max.
Maximum BUSY active time (write
access)
See important note 1
68 ns - - 68 ns -
t
5
t
DVR min.
Minimum Time between valid data
bus signals and rising edge of BUSYn
signal 7,8 ns 8.3 ns 5 ns 7,8 ns 5 ns
t
6
t
DSW min.
Minimum setup time for write data 10.8 ns 12.1 ns 25 ns 12.8 ns 25 ns
t
7
t
DHR min.
Minimum read data hold time 2.1 ns 1.5 ns 0 ns 2.1 ns 0 ns
t
8
t
DHW min.
Minimum hold time for write data 0.8 ns 0 ns 0 ns 2.8 ns 2.8 ns
t
9
t
AHR min.
Minimum address hold time 0 ns 0 ns 0 ns 0 ns 0 ns
t
10
t
AHW min.
Minimum address hold time 0.9 ns 0 ns 0 ns 2.9 ns 2.9 ns
t
11
t
RWI
Minimum inactive time for RDn or
WRn 10.5 ns 10 ns 10 ns 12.5 ns 12.5 ns
Table 37: Symbols for COMX Timing Diagram for Read and Write Access
Important Note 1:
Avoid dual-port memory access errors
It is mandatory that the host CPU always uses the
DPM_BUSYn
signal, otherwise
this results in wrong data read from the dual-port memory or dual-port memory
write accesses are ignored. This does not affect
COMX10
und
COMX51
!

The maximum value for accesses cannot be specified.

For maximum performance, the
DPM_BUSYn
signal must always be evaluated
by the host CPU.

If you use a host CPU that cannot use the
DPM_BUSYn
signal, then contact our
technical support.
Note 2: The value for t
BAR
typ. (t
3
typ.) depends on the used firmware/application on the netX.
Note 3:
DPM_BHEn
is only used for 16 bit interface.