Guardian G25AMK005, Техническое руководство

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G U A R D I A N V H F 1 1 0 W M O B I L E 3-3
The DSP pages-in different program images from the Flash for different modes of operation. Typically one image is
used for receive and standby modes, but a new image is needed for transmit and key management operations. The
DSP can interrupt the H8 controller, and then pass data over the host port back to H8. Interrupts from the DSP
include the following events:
•
Signal detected with type data
•
Signal lost
•
DSP BIT errors
•
Paging request
In all active modes the H8 software must be able to write a number of parameters to the DSP and also read back a
number of parameters from the DSP. This is implemented through the host port. The parameters used include:
Mode Description
Search
Reference oscillator temperature used by DSP to correct frequency offsets. AGC
reset control is used at start of search period
Analog setting BW, squelch tones, squelch code, and squelch level
Digital setting Data rate, key, and algorithm
Project 25 setting NAC and TGID
CVSD setting Continuously variable slope delta (CVSD). Data rate
Receive Reference oscillator temperature used by DSP to correct frequency offsets. Audio
volume
Analog setting Squelch controls, de-emphasis, and companding
Digital setting Data rate and key algorithm
Project 25 setting NAC, TGID, BER, and test mode
CVSD setting Data rate and key
Project 25 setting Read by H8: SS bits, low-rate data (for future use), and sender ID
Transmit Reference oscillator temperature used by DSP to correct frequency offsets. Audio
volume, sidetone on/off
Analog setting Squelch controls and de-emphasis
CVSD setting Data rate and key
Project 25 setting NAC, TGID, key and low-rate data (for future use)
3.2.3 Transceiver Board
The Transceiver board is controlled through a synchronous serial bus from H8 to the transceiver allowing H8 to
control the synthesizer, two 4-channel 8-bit digital to analog converters (DAC), and a control shift register in the
transceiver board. Some of the DAC channels are set according to data in the transceiver’s electronically erasable
read-only memory (EEPROM) calibration tables.
3.2.3.1 Mode Control
The transceiver shift register and the CTX output of the field-programmable gate array (FPGA) control the modes of
operation (transmit, receive, or standby). The outputs are controlled as below:
Mode Description
Spare (SR bit 1) Spare
3.3VRXSynth (SR bit 2) Set in active receive mode, RXVCO enable
3.3VTXSynth (SR bit 3) Set in active transmit mode, TXVCO enable
3.3VRXEnable (SR bit 4) Set in active receive mode, receiver enable
Spare (SR bit 5)
Spare
Spare (SR bit 6) Spare