Guardian G25AMK005, Техническое руководство

Страница: 23 / 85

G U A R D I A N V H F 1 1 0 W M O B I L E 2-13
2.5.3 Digital/Analog Control
Digital/analog control is shown on page 1 of the RECM schematic. The transceiver is fitted with an EEPROM
(U15). The IC is used to store calibration and curve fit data, which is needed when the transceiver is configured
with the Guardian radio. Each transceiver has its calibration and curve fit data stored within the EEPROM. The
calibration and curve fit data is written to the EEPROM at the successful conclusion of level 2 testing. Two quad 8-
bit serial DACs, a quad 12-bit serial DAC, and supporting operational-amplifiers (U2, U6, U13, U18, and U30)
control much of the transceiver, as has been discussed previously. U32 is a 2.5 Vdc reference used by the Quad 12-
bit DAC and the variable IF attenuator (discussed previously).
U18D and associated components amplifies the dc signal supplied by U31-3.
As was discussed previously, REFOSCMOD is the dc signal, which varies the operating frequency of the reference
oscillator. Normally under DSP and microprocessor control, this line is used to FM modulate the reference
oscillator, which in turn FM modulates the RF carrier in transmit mode. This line is used to temperature compensate
the reference oscillator as well.
The DAC controlled line TXVCOMOD at U31-4 is transmit data normally controlled by DSP and a microprocessor.
This signal is routed to U18C and associated components. U18C and associated components form an active
LPF/attenuator to shape the transmit data before modulating the RF carrier in the transmit mode.
The cutoff
frequency of the LPF occurs at 20 kHz. The 1 kHz peak-to-peak signal level at the active LPF output (U18-8) is
one-fourth TXVCOMOD at 2.5 Vdc.
The synthesizer reference oscillator and the transmit VCO are simultaneously modulated to balance the FM
modulation. We refer to this technique as two-point modulation. The DAC values required to balance the
modulation are dependent on RF frequency.
The dc signal at U31-17 is routed to U30 and associated components. This op-amp is configured for a voltage gain
of 2. The dc signal VATT controls the variable IF attenuator (discussed previously) in the receiver chain. Under
DSP and microprocessor control, the attenuator is normally set for a desired amount of attenuation by this DAC
controlled signal.
Q37, Q38, Q39, Q40, Q41, and associated components are used to enable and disable the 14 dB step attenuator in
the receiver chain (discussed previously). Normally under DSP and microprocessor control, the attenuator is set to
the desired state of operation via U31-13. A logic level “1” at this pin enables the attenuator. Conversely, a logic
level “0” at this pin disables the attenuator (bypass mode).
U18B and associated components amplifies the dc signal supplied by U33-2. As discussed previously, CTUNE is
the dc signal which coarse tunes the receive and transmit VCOs. Under microprocessor control, the appropriate
VCO is normally coarse tuned to a desired frequency based on curve fit data stored in the EEPROM (U15). Curve
fit data is obtained and stored in the EEPROM during coarse tune calibration procedures performed at level 2
testing.
The DAC controlled DC signal 2
nd
LO sets the 2
nd
LO (discussed previously) on frequency at 44.545 MHz.
Normally under microprocessor control, the 2
nd
LO is set on frequency based on a DAC value stored in the
EEPROM (U15). The correct DAC value is obtained and stored in the EEPROM during the 2
nd
LO calibration
procedure at level “2” testing.
The DAC controlled dc signal RXVTF appropriately sets the varactor tuned BPF (discussed previously) based on
the receiver tuned frequency. Normally under microprocessor control, the varactor tuned BPF is set based on curve
fit data stored in the EEPROM (U15). The curve fit is based on statistical data obtained during the testing of
hundreds of units.
The DAC controlled dc signal PWRSET sets the power amplifier (discussed previously) to a desired power level.
Normally under microprocessor control, the power amplifier is set to the desired level based on curve fit data stored
in the EEPROM (U15). The curve fit data is obtained and stored in the EEPROM during transmit power calibration
procedures at level 2 testing. The power calibration procedure obtains curve fit data for five power level settings
(0.1W, 0.5W, 1.0W, 2.0W, and 5.W) over the entire transmitter operating frequency range (136 to 174 MHz).
The DAC controlled dc signals PA1 and PA2 set the gate bias for each power transistor (Q6 and Q9 respectively) in
the power amplifier circuit (discussed previously). These two signals are routed to op-amps U2 and U6, which are