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GOWIN DK START GW1NZ-LV1FN32C6I5 Скачать руководство пользователя страница 2

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Содержание DK START GW1NZ-LV1FN32C6I5

Страница 1: ...DK_START_GW1NZ LV1FN32C6I5_V3 1 User Guide DBUG393 1 0E 07 22 2021 ...

Страница 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Страница 3: ...Revision History Date Version Description 07 22 2021 1 0E Initial version published ...

Страница 4: ... 2 2 Introduction 3 2 1 Overview 3 2 2 Development Kit 4 2 3 PCB Components 5 2 4 System Block Diagram 5 2 5 Features 6 2 6 Development Board Description 7 3 Development Board Circuit 8 3 1 FPGA Module 8 3 2 Download 8 3 2 1 Overview 8 3 2 2 USB Download Circuit 9 3 2 3 Download Flow 9 3 2 4 Pinout 9 3 3 Power Supply 9 3 3 1 Overview 9 3 4 Clock Reset 10 3 4 1 Overview 10 3 4 2 Clock Reset Circuit...

Страница 5: ... 11 3 5 1 Overview 11 3 5 2 LED Circuit 11 3 5 3 Pinout 11 3 6 Switches Module 12 3 6 1 Overview 12 3 6 2 Switches Circuit 12 3 6 3 Pinout 12 3 7 GPIO 13 3 7 1 Overview 13 3 7 2 GPIO Circuit 13 3 7 3 Pinout 13 4 Considerations 15 5 Gowin Software 16 ...

Страница 6: ...V1FN32C6I5_V3 1 Development Board 3 Figure 2 2 A Development Kit 4 Figure 2 3 PCB Components 5 Figure 2 4 System Block Diagram 5 Figure 3 1 FPGA USB Download Diagram 9 Figure 3 2 Clock Reset 10 Figure 3 3 LED Circuit 11 Figure 3 4 Switches Circuit 12 Figure 3 5 GPIO Circuit 13 ...

Страница 7: ...ables Table 1 1 Terminology and Abbreviations 1 Table 2 1 Development Board Description 7 Table 3 1 FPGA Download Pinout 9 Table 3 2 FPGA Clock and Reset Pinout 10 Table 3 3 LED Pinout 11 Table 3 4 Switches Pinout 12 Table 3 5 GPIO Pinout 13 ...

Страница 8: ...lopment software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS841 GW1NZ series of FPGA Products Data Sheet 2 UG843 GW1NZ series of FPGA Products Package and Pinout User Guide 3 UG842 GW1NZ 1 Pinout 4 UG290 Gowin FPGA Products Programming and Configuration Guide 5 SUG100 Gowin Software User Guide 1 3 ...

Страница 9: ...Static Random Access Memory PLL Phase locked Loop LVDS Low Voltage Differential Signaling DSP Digital Signal Processing SPMI System Power Management Interface FN32 QFN32 package 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website w...

Страница 10: ...s of FPGA device The GW1NZ series of FPGA products are the first generation products in the LittleBee family It has the characteristics of low power consumption instant on low cost non volatile high security various packages and flexible usage They can be widely used in communication industry control consumption video control etc GOWINSEMI provides a new generation of FPGA hardware ...

Страница 11: ...interface GPIO interfaces SPMI keys LEDs etc which is useful for both developers and learners 2 2 Development Kit The development board kit includes the following items DK_START_GW1NZ LV1FN32C6I5_V3 1 development board 5V power Input 100 240V 50 60Hz 0 5A output DC 5V 2A USB Mini B cable Figure 2 2 A Development Kit 1 2 3 DK_START_GW1NZ LV1FN32C6I5_V3 1 development board 5V power supply USB Mini B...

Страница 12: ...2 GPIO DONE Voltage Selection OSC FPGA Dial Switch SPMI Test Pin SPMI JTAG Selection Level Conversion Chip USB Download USB to JTAG Chip Power Chip 3 2 4 System Block Diagram Figure 2 4 System Block Diagram LED Crystal Oscillator USB DONE Light 20PIN GPIO Header X17 Reset X9 X4 X1 X1 X2 X4 Dial Switch Slide Switch X1 GW1NZ LV1FN32C6 I5 ...

Страница 13: ...ies of SSRAM Supports LV and UV Embedded SPMI 2 FPGA Configuration Mode JTAG AUTO BOOT DUAL BOOT 3 Clock resource 12MHz Clock Crystal Oscillator 50MHz Clock Crystal Oscillator 4 Key One reset key 5 Switches 1 9 bit dip switch 4 slide switch 6 LED 1 power indicator green 1 DONE indicator 2 LEDs green 7 Memory device 64Kbit built in Flash 8 GPIO 17 I Os 9 LDO Power Inverse voltage protection overcur...

Страница 14: ... the 5V to 3 3 V circuit Provides power for FPGA via 5V to 1 8V circuit Provides power for FPGA via 3 3V to 0 9V 1 2V circuit 4 Switches Available for SPMI test 4 5 Dip switch Available for multiplexing IO test 1 6 Reset key FPGA reset 1 7 LED Test indicator DONE indicator Power indicator 2 test indicators green 1 DONE indicator green 1 Power indicator green 8 Crystal Oscillator Provide 12MHz 50MH...

Страница 15: ...mation see UG843 GW1NZ Series of FPGA Products Package and Pinout User Guide 3 2 Download 3 2 1 Overview The development board provides an USB download interface The bitstream file can be downloaded to the internal SRAM or internal flash as needed Note When downloaded to SRAM the bitstream file will be lost if the device is powered down and it will need to be downloaded again after power on If dow...

Страница 16: ...ash When the Done is on it indicates that the download has been successful 3 2 4 Pinout Table 3 1 FPGA Download Pinout Name Pin No BANK Description I O Level TDI 3 0 JTAG Signal 1 8V 3 3V TCK 6 0 JTAG Signal 1 8V 3 3V TMS 7 0 JTAG Signal 1 8V 3 3V TDO 1 0 JTAG Signal 1 8V 3 3V 3 3 Power Supply 3 3 1 Overview The development board is powered via a power adapter The input parameter is 100 240V 50 60...

Страница 17: ...f PLL can provide clocks required by users Note DK_START_GW1NZ LV1FN32C6I5_V3 1 development board provides 50MHz clock input The crystal oscillator input provided by the development board depends on the FPGA device on the board 3 4 2 Clock Reset Circuit Figure 3 2 Clock Reset 3 4 3 Pinout Table 3 2 FPGA Clock and Reset Pinout Name Pin No BANK Description I O Level FPGA_CLK 19 1 Active crystal osci...

Страница 18: ...h LEDs To use them the LED1 and LED2 of S1 must be set to ON You can test the LEDs in the following ways When the FPGA corresponding pin output signal is logic low the LED is lit If the signal is high LED is off 3 5 2 LED Circuit Figure 3 3 LED Circuit 3 5 3 Pinout Table 3 3 LED Pinout Name Pin No BANK Description I O Level F_LED1 14 1 LED 1 1 8V 3 3V F_LED2 12 1 LED 2 1 8V 3 3V ...

Страница 19: ...t board available for SPMI test Set to SPMI JTAG is multiplexed to SPMI Set to JTAG it is JTAG download 3 6 2 Switches Circuit Figure 3 4 Switches Circuit 3 6 3 Pinout Table 3 4 Switches Pinout Signal Name Pin No BANK Description I O Level SPMI_TCK 6 0 SPMI 1 8V 3 3V SPMI_TDO 1 0 SPMI 1 8V 3 3V SPMI_TMS 7 0 SPMI 1 8V 3 3V SPMI_TDI 3 0 SPMI 1 8V 3 3V ...

Страница 20: ...tion extension and testing 3 7 2 GPIO Circuit Figure 3 5 GPIO Circuit 3 7 3 Pinout Table 3 5 GPIO Pinout Signal Name Pin No 20P Socket Pin No BANK Description I O Level H_A_IO1 32 1 0 General I O 1 8V 3 3V H_A_IO2 31 2 0 General I O 1 8V 3 3V H_A_IO3 30 3 0 General I O 1 8V 3 3V H_A_IO4 29 4 0 General I O 1 8V 3 3V H_A_IO5 2 5 0 General I O 1 8V 3 3V ...

Страница 21: ...8 25 8 0 General I O 1 8V 3 3V H_A_IO9 24 9 1 General I O 1 8V 3 3V H_A_IO10 23 10 1 General I O 1 8V 3 3V H_A_IO11 22 11 1 General I O 1 8V 3 3V H_A_IO12 21 12 1 General I O 1 8V 3 3V H_A_IO13 20 13 1 General I O 1 8V 3 3V H_A_IO14 18 14 1 General I O 1 8V 3 3V H_A_IO15 17 15 1 General I O 1 8V 3 3V H_A_IO16 16 16 1 General I O 1 8V 3 3V H_A_IO17 15 17 1 General I O 1 8V 3 3V GND 18 GND 19 GND 20...

Страница 22: ...et SW2 SW3 SW4 SW5 to JTAG Download fs file then power off Set to SPMI power on again to test and debug 3 J2 and J3 on the board are VCCX and VCCIO power selection You can select 1 8V or 3 3V 4 In the normal use of the development board it is necessary to switch all the nine switches of S1 to ON 5 When testing the static power consumption nine switches of the S1 need to be turned off ...

Страница 23: ...5 Gowin Software DBUG393 1 0E 16 16 5 Gowin Software See SUG100 Gowin Software User Guide for details ...

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