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3 Development Board Circuit 3.4 Clock, Reset
DBUG393-1.0E 10(16)
3.4 Clock, Reset
3.4.1 Overview
The development board provides a 12MHz/50MHz 1 crystal oscillator
connected to the GCLK input pin. This can be employed as the global clock.
Frequency division and multiplication of PLL can provide clocks required by
users.
Note!
DK_START_GW1NZ-LV1FN32C6I5_V3.1 development board provides 50MHz clock input.
The crystal oscillator input provided by the development board depends on the FPGA
device on the board.
3.4.2 Clock, Reset Circuit
Figure 3-2 Clock, Reset
3.4.3 Pinout
Table 3-2 FPGA Clock and Reset Pinout
Name Pin No. BANK Description I/O Level
FPGA_CLK 19 1
Active crystal
oscillator Input
1.8V/3.3V
FPGA_RST2_N 11 1
Reset Signal,
active-low
1.8V/3.3V