3 Development Board Circuit
3.9 MIPI/LVDS
DBUG361-1.2E
27(30)
Table 3-13 J16 FPGA Pin Distribution (IDES16:1 Supported)
Signal Name
Pin No.
Socket Pin No.
BANK Description
I/O Level
F_LVDS_B1_P
29
1
2
Differential
output channel
1+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_B1_N
30
2
2
Differential
output channel
1-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
3
-
-
-
GND
-
4
-
-
-
F_LVDS_B2_P
38
5
2
Differential
output channel
2+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_B2_N
39
6
2
Differential
output channel
2-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
7
-
-
GND
-
8
-
-
F_LVDS_B3_P
42
9
2
Differential
output channel
3+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_B3_N
43
10
2
Differential
output channel
3-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
11
-
-
GND
-
12
-
-
F_LVDS_B4_P
46
13
2
Differential
output channel
4+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_B4_N
47
14
2
Differential
output channel
4-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
15
-
-
GND
-
16
-
-
F_LVDS_B5_P
50
17
2
Differential
output channel
5+
2.5V(LVDS)/
1.2V(MIPI)
F_LVDS_B5_N
51
18
2
Differential
output channel
5-
2.5V(LVDS)/
1.2V(MIPI)
GND
-
19
-
-
Содержание DK-START-GW1NR9
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