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8. Timing Chart
●
Pixel clock timing (common in various operation modes)
(Note) The above timing represents the signal timing before being input to the input part of the GigE interface unit (Camera
Link interface).
All the synchronization signals described in this section are internal signals as the synchronization signal
(FVAL,LVAL,CLK etc.) is not output to the outside in the case of GigE camera.
(Note) The image signals which are input into Camera Link interface through two taps(CH1,CH2) are output from LAN
connector as the image data after forming successive single image in the GigE interface.
(!) In the case of Fx11000GE, the image signals are output in order from the left even in DUAL output mode (5fps) as they are
sorted using internal buffer
Output form when in DUAL scanning
１ＣＬＫ＝３０．８ｎＳ
１０ｎｓ(max)
Cl o ck ou tp u t
Di g it a l da t a
Ｃ Ｈ １ ／ Ｃ Ｈ ２
１ ０ o r ８ o r １ ２ b it
CLK
Ａ／Ｄ
Ｌ Ａ Ｎ
co n ne ct or
C
h
an
n
el
L
in
k
(LVAL,FVAL)
G
ig
E
I/
F
DEMULTIPLEX.
10/8/12bit
10/8/12bit
CH1
CH2
PCLK
1／1
CLK
Ａ／Ｄ
R
J-
4
5
8～12bit
8～12bit
[Phase relationship between clock output and data]
有 効 撮 像 領 域
Ｖ
ta p1
(F ro m t h e le f t)
t ap 2
( Fr o m t he r i gh t )
Ima ging ar ea
O ut pu t d i re ct i on
O u tp u t di r ec t io n
Co nve ntio nal camera：e.g.FC5100CL 15 fps (DUA L)
有 効 撮 像 領 域
Ｖ
Camera Link
output
Ta p 1( Fr o m t he l e ft ； O d d nu m be r )
Ta p 2( Fr o m t he l e ft ； E v en n u mb e r)
Imaging area
Ou t pu t d ir e ct i on
FC11000CL
5fps(DUAL)
Ev en num bere d p ixe l
Od d-n umb ered pi xel
So rt i ng
C amera Link
o utput
