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VPC5000 Series Vehicle PC Installation Manual ver.A.1
6.3.1 DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is By
SPD.
6.3.2 CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The system board
designer should set the values in this field, depending on the DRAM installed. Do not
change the values in this field unless you change specifications of the installed DRAM or
the installed CPU.
6.3.3 Active to Precharge Delay
The default setting for the Active to Precharge Delay is 7.
6.3.4 DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and
CAS (Column Address Strobe) signals.
This delay occurs when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
6.3.5 DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge
before the SDRAM refreshes.
The default setting for the Active to Precharge Delay is 3.
6.3.6 On-Chip VGA
The default setting is enabled.
6.3.7 On-Chip Frame Buffer Size
The default setting is 32MB.
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6.4 Integrated
Peripherals
This section sets configurations for your hard disk and on board devices.
Figure 6.4.1: Integrated Peripherals screen
Figure 6.4.2 on Chip IDE Device
