General Standards Corporation PCIe-24DSI32, Справочное руководство

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PCIe-24DSI32
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General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: solutions@GeneralStandards.com
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LIST OF ILLUSTRATIONS
FIGURE
TITLE

PAGE
1.1 Physical Configuration 1-1
1.2 Functional Organization 1-2
2.2.2 System I/O Connections 2-2
2.3.1 Input Configurations 2-3
2.4.1 Multiboard Clock/Sync Connections 2-4
2.6.2 Reference Adjustment Access 2-6
3.6.1.1 ADC Clock and Sync Organization, 32 Channels 3-9
4.1 Functional Block Diagram 4-1
LIST OF TABLES
TABLE TITLE __

PAGE
2.2.2 System Connector Pin Assignments 2-2
2.6.1 Reference Adjustment Equipment 2-6
3.1 Control and Data Registers 3-1
3.2 Board Control Register 3-2
3.3.1 Configuration Operations 3-3
3.4 Analog Input Function Selection 3-4
3.4.3 Analog Input Range Selection 3-4
3.5.2 Input Data Buffer Organization 3-5
3.5.2.2 Analog Input Data Coding; 16-Bit Data Field 3-6
3.5.3 Buffer Control Register 3-6
3.6.1.1 Channel Groups 3-9
3.6.1.2-1 Rate Assignments Register 3-10
3.6.1.2-2 Rate Generator Assignment Codes 3-10
3.6.1.3 Rate Divisor Register 3-10
3.6.2.1-1 PLL Nref Register 3-12
3.6.2.1-2 PLL Nvco Register 3-12
3.6.2.1-3 Summary of PLL Sample Rate Control Parameters 3-12
3.6.2.2-1 Legacy Rate Control Register 3-14
3.6.3 Direct External Clocking 3-14
3.8.1 Interrupt Event Selection 3-18
3.9.1 Typical DMA Register Configuration; Block Mode 3-16
3.9.2 Typical DMA Register Configuration; Demand Mode 3-16
3.10.1 Channel Order 3-20
3.11.1 Board Configuration Register 3-22