PCIe-24DSI32
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General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: [email protected]
3-3
3.3 Configuration and Initialization
3.3.1 Board Configuration
Board configuration is initiated by a PCIe bus RESET, and should be required only once after
the initial application of power. During board configuration, initial values for both the PCIe
configuration registers and the internal control logic are extracted from internal nonvolatile read-
only memory. While the PCIe configuration registers are being loaded, the response to PCIe
target accesses is RETRY's. Configuration operations are executed in the sequence shown in
Table 3.3.1.
Table 3.3.1. Configuration Operations
Operation
Maximum Duration
PCI configuration registers are loaded from internal EEPROM
3 ms
Internal control logic is configured from internal ROM
300 ms
Internal control logic is initialized
3 ms
A/D converters and clocks are initialized
5 seconds
Board configuration terminates with the PCIe interrupts disabled. Attempts to access the local
bus during configuration should be avoided until the PCIe interrupts are enabled and the
initialization-complete interrupt request is asserted.
3.3.2 Initialization
Internal control logic can be initialized without invoking configuration by setting the INITIALIZE
control bit in the BCR. This action causes the internal logic to be initialized, but does not affect
the PCIe configuration registers and does not reconfigure the internal control logic. Initialization
has a maximum duration of 5 seconds, and produces the following conditions:
The Initiator mode is selected, External clock output is Channel-00 sample clock,
The width of the buffer data field is adjusted to 16 bits,
The internal rate generator is the ADC clock source,
Internal rate generator frequency is 32.768 MHz,
Rate divisor(s) are preset to 5,
Sample rate is 12.8 KSPS; i.e.: 32.768MHz / (512 *5).
The analog input buffer is reset to empty; buffer threshold equals 0003 FFFEh,
Analog inputs are configured for ±10 Volt operation,
All control registers are initialized; all defaults are invoked,
The local interrupt request is asserted as an initialization-completed event.
Upon completion of initialization, the INITIALIZE control bit is cleared automatically.
