Cinterion
®
ELS31-VA/ELS51-VA Hardware Interface Description
3.2 Power Up/Power Down Scenarios
76
ELS31-VA_ELS51-VA_HID_v01.000
2017-01-04
Confidential / Preliminary
Page 62 of 106
3.2.3
Signal States after First Startup
lists the states each interface signal passes through during reset and first firmware
initialization. For further firmware startup initializations the values may differ because of differ-
ent GPIO line configurations.
The reset state is reached with the rising edge of an internal reset line - either with a normal
module startup after about 26 milliseconds (see
) or after a restart (see
). After the reset state has been reached the firmware initialization state begins. The firm-
ware and command interface initialization is completed as soon as the ASC0 interface line
CTS0 has turned low (see
). Now, the module is ready to receive and transmit data.
Abbreviations used in above
Table 15:
Signal states
Signal name
Default functionality
Reset state
First start up configuration
CCIO
I
O / L
CCRST
I
O / L
CCCLK
O / L
O / L
CCIN
I
I / PD
RXD0
I / PU
O / H
TXD0
I
I
CTS0
I
O / H
RTS0
I
I / PD
GPIO1/DTR0
DTR0
T / PD
I / PU
GPIO2/DCD0
DCD0
T / PD
O
GPIO3/DSR0
DSR0
T / PD
O
GPIO4/FST_SHDN
GPIO4
I / PD
I / PU
GPO5/LED
LED
I / PD
O
GPIO6
GPIO6
I / PD
I / PD
GPIO7
GPIO7
I / PU
I / PD
GPIO8/COUNTER
GPIO8
I
I / PD
GPIO16/RXD1
GPIO16
I
I / PU
GPIO17/TXD1
GPIO17
I /PU
I / PU
GPIO18/RTS1
GPIO18
I /PU
I / PU
GPIO19/CTS1
GPIO19
I /PU
I / PU
GPIO20/PCM_I2S_OUT GPIO20
I
I / PD
GPIO21/PCM_I2S_IN
GPIO21
I
I / PD
GPIO22/PCM_I2S_FSC GPIO22
I
I / PD
GPO23/PCM_I2S_CLK
GPO23
I
O / L
GPIO24/RING0
RING0
T / PD
O
GPIO25
GPIO25
I
I / PD
GPO26/SPI_CS1
GPO26
I
O
GPIO27/SPI_CS2
GPIO27
I
I / PD
I2CCLK
I / PD
T / OD
I2CDAT
I / PD
T / OD
L = Low level
H = High level
T = Tristate
I = Input
O = Output
OD = Open Drain
PD = Pull down
PU = Pull up