18 IMP2B 3U cPCI Single Board Computer
Publication No. IMP2B-0HH/5
3.3 RAM
The IMP2B supports up to 1 GByte of DDR2 SDRAM, with 512 MBytes fitted as
standard. This is configured as a single bank (512 MBytes) or two banks (1 GByte) of
contiguous 64-bit wide memory, and is interfaced to the memory controller in the
MV64560 by a 64-bit data bus running at 200 MHz (DDR2-400).
The following table shows the RAM options available for the IMP2B:
Table 3-1 SDRAM Options
SDRAM Size (MBytes) Banks SDRAM Device Organization
512
1
64M x 16
1024
2
64M x 16
The RAM array is protected by an 8-bit ECC, capable of detecting all single-bit,
double-bit and nibble errors, and correcting single bit errors.
CAUTIONS
The second DDR2 RAM bank physically resides in the PMC ‘Keep-Out’ area. When the IMP2B is fitted
with 1 GByte of DRAM memory, the available component height in the PMC ‘Keep-Out’ region for an
install PMC is reduced from 10mm to 5mm.
Integrity of SDRAM data cannot be guaranteed during hard reset, since the memory controller is reset
and SDRAM refresh disabled.
3.4 Non-Volatile RAM (NVRAM)
A 128 KByte Simtek STK14CA8 AutoStore NVRAM is provided for non-volatile set-
up and configuration data storage. The NVRAM is configured as an 8-bit wide
device, accessed using the device bus at DEV_CS2. For more details, see the data
sheet.
LINK
http://www.simtek.com/product-selector-guide.htm
The NVRAM is write-protected by the
NVRAM Write Enable Link (P5 3-4)
. The
