GE D30 series, Инструкция по эксплуатации

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8-6 D30 LINE DISTANCE PROTECTION SYSTEM – INSTRUCTION MANUAL
SERIES COMPENSATED LINES CHAPTER 8: APPLICATION OF SETTINGS
8
A line compensating capacitor is a bank of three physical capacitors and their overvoltage protecting devices (air gaps
and/or MOVs). If none of the MOV/gaps conducts any significant current, the positive-, negative- and zero-sequence
reactance of the three-phase bank equal the reactance of the actual (phase) capacitors. Under asymmetrical conditions,
however, such as a single line to ground fault, when only one MOV/gap can operate, the series capacitor bank creates
extra (series) asymmetry in addition to the fault (shunt) asymmetry. The positive-, negative- and zero-sequence
impedances differ from each other and do not equal the impedance of the phase capacitors. Moreover, there can be
mutual coupling between the sequence networks representing the series capacitor bank. This makes analytical analysis of
fault conditions burdensome. For setting calculations, however, it is justified to assume the zero-, positive-, and negative-
sequence reactance of the capacitor bank equal the reactance of the actual (phase) capacitors. This represents a worst-
case low-current fault scenario, when the steady-state effects of series compensation are most weighty.
8.3.2 Distance
Traditionally, the reach setting of an underreaching distance function is set based on the net inductive impedance
between the potential source of the relay and the far-end busbar, or location for which the zone must not overreach. Faults
behind series capacitors on the protected and adjacent lines need to be considered for this purpose. For further
illustration, a sample system shown in the figure is considered.
Figure 8-2: Sample series-compensated system
Assuming 20% security margin, the underreaching zone is set as follows.
At the Sending Bus, consider an external fault at F1 because the 5
Ω
capacitor contributes to the overreaching effect. Any
fault behind F1 is less severe as extra inductive line impedance increases the apparent impedance:
Reach Setting: 0.8 x (10 – 3 – 5) = 1.6 Ω if the line-side (B) VTs are used
Reach Setting: 0.8 x (10 – 4 – 3 – 5) = –1.6 Ω if the bus-side (A) VTs are used
The negative value means that an underreaching zone cannot be used as the circuit between the potential source of the
relay and an external fault for which the relay must not pick-up, is overcompensated, for example capacitive.
At the Receiving Bus, consider a fault at F2:
Reach Setting: 0.8 x (10 – 4 – 2) = 3.2 Ω if the line-side (B) VTs are used
Reach Setting: 0.8 x (10 – 4 – 3 – 2) = 0.8 Ω if the bus-side (A) VTs are used
Practically, however, to cope with the effect of sub-synchronous oscillations, one can need to reduce the reach even more.
As the characteristics of sub-synchronous oscillations are in complex relations with fault and system parameters, no solid
setting recommendations are given with respect to extra security margin for sub-synchronous oscillations. It is strongly
recommended to use a power system simulator to verify the reach settings or to use an adaptive D30 feature for dynamic
reach control.
If the adaptive reach control feature is used, set the
PHS DIST Z1 VOLT LEVEL
setting accordingly.
This setting is a sum of the overvoltage protection levels for all the series capacitors located between the relay potential
source and the far-end busbar, or location for which the zone must not overreach. The setting is entered in pu of the phase
VT nominal voltage (RMS, not peak value).