Fujitsu MB90390 Series, Руководство по оборудованию

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CHAPTER 5 CLOCKS
5.3.1 Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and a
PLL clock and is also used to select an oscillation stabilization wait time and a PLL
clock multiplier.
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Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-2 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-2 Configuration of the Clock Selection Register (CKSCR)
Note:
The machine clock selection bit is initialized to main clock selection at a reset.
MCM
0
1
MC S
0
1
W S 1 W S 0
0
0
1
1
0
1
0
1
C S 1
1
C S 0
M u ltiplier s election b it s
The re su lting clock for 4 a nd 5 MHz cry s t a l
The corre s ponding time interv a l for a n o s cill a tion clock
of 4 MHz / 5 MHz i s given in p a renthe s e s .
M a chine clock s election b it
0
0
1
1
0
1
0
1
1 x HCLK (4MHz / 5 MHz)*
2 x HCLK ( 8 MHz / 10 MHz)*
3 x HCLK (12MHz / 15 MHz)*
4 x HCLK (16MHz / 20 MHz)*
2
10
/ HCLK(Approx. 256/204. 8
μ
s )
PLL clock s elected.
M a in clock s elected.
M a chine clock indic a tion b it
W S 0
0
(LPMCR)
Re s erved Re s erved
C S 1
C S 0
MC S MCM W S 1
Addre ss :
b it
Initi a l v a l u e
R/W R/W R R/W R/W R/W R/W R/W
0 0 0 0 A 1
H
1 1 1 1 1 1 0 0
B
MCM
R u nning on a PLL clock.
R u nning on the m a in clock.
2
7
/ HCLK (Aprox. 3 2.77/26.22
2
15
/ HCLK (Aprox. 8 .19/6.55
2
1 3
/ HCLK (Aprox. 2.05/1.64
HCLK
R/W
R : O s cill a tion clock
: Re a d ab le a nd writ ab le
: Re a d only
: Initi a l v a l u e
O s cill a tion s t ab iliz a tion w a it time s election b it s
15 14 1 3 12 11 10 9 8
i s given in p a renthe s e s .
* If a power-on re s et occ u r s the o s cill a tion s t ab iliz a tion
a it time i s 2
1 8
/HCLK ( a pprox. 65.54 m s ).
m s )
m s )
m s )*
0
0
1
1
0
1
0
1
2 x HCLK ( 8 MHz / 10 MHz)
4 x HCLK (16MHz / 20 MHz)
6 x HCLK (24MHz / S et u p Prohi b ition)
Prohi b ition
C S 2
0
0
0
0
1
1
1
1
*: The s etting exceeded 20MHz i s di sab led.
C S 2(PLLC regi s ter: b it 8 )