Fujitsu MB15F74UV Скачать руководство пользователя страница 16 | Manualshive

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MB15F74UV

16

2.

OSC

IN

input sensitivity

10

0

20

40

80

100

140

160

V

CC

=

2.7 V

V

CC

=

3.0 V

V

CC

=

3.6 V

SPEC

0

−

10

−

20

−

30

−

40

−

50

60

120

Catalog guaranteed
range

Input sensitivity vs. Input frequency

Input

frequency f

OSC

(MHz)

Input sensitivity V

OSC

(dBm)

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Содержание MB15F74UV

Страница 1: ...mA at 3 0 V The supply voltage range is from 2 7 V to 3 6 V A refined charge pump supplies well balanced output current with 1 5 mA and 6 mA selectable by serial date The serial data format is the same as MB15F74UL Fast locking is achieved for adopting the new circuit MB15F74UV is in the small package BCC18 which decreases a mount area of MB15F74UV about 50 com paring with the former BCC20 for dua...

Страница 2: ...7 bit swallow counter 0 to 127 Binary 11 bit programmable counter 3 to 2 047 Built in high speed tuning low noise phase comparator current switching type constant current circuit On chip phase control for phase comparator On chip phase comparator for fast lock and low noise Built in digital locking detector circuit to detect PLL locking and unlocking Operating temperature Ta 40 C to 85 C Serial da...

Страница 3: ...pin must be set at L when the power supply is started up Open is prohibited PSRF H Normal mode PSRF L Power saving mode 10 DoRF O Charge pump output for the RF PLL section 11 VCCRF Power supply voltage input pin for the RF PLL section 12 GNDRF Ground pin for the RF PLL section 13 XfinRF I Prescaler complimentary input pin for the RF PLL section This pin should be grounded via a capacitor 14 finRF ...

Страница 4: ...itch 2 bit latch 14 bit latch 1 bit latch Binary 14 bit pro grammable ref counter IF PLL C P setting counter Lock Det IF PLL 2 bit latch 14 bit latch 1 bit latch Binary 14 bit pro grammable ref counter RF PLL C P setting counter Selector Prescaler RF PLL 64 65 128 129 Lock Det RF PLL Intermittent mode control RF PLL 3 bit latch FC IF SW IF LDS 3 bit latch 7 bit latch 11 bit latch Binary 7 bit swal...

Страница 5: ... it from the socket turn the power supply off When handling such as transporting the device mounted board protect the leads with a conductive sheet WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semico...

Страница 6: ... voltage VIL Schmitt trigger input 0 3 VCC 0 4 V H level input voltage PSIF PSRF VIH 0 7 VCC V L level input voltage VIL 0 3 VCC V H level input current Data LE Clock PS IIH 4 1 0 1 0 µA L level input current IIL 4 1 0 1 0 µA H level output voltage LD fout VOH VCC 3 0 V IOH 1 mA VCC 0 4 V L level output voltage VOL VCC 3 0 V IOL 1 mA 0 4 V H level output voltage DoIF DoRF VDOH VCC 3 0 V IDOH 0 5 m...

Страница 7: ...ction of current flow 5 VCC 3 0 V Ta 25 C I3 I4 I3 I4 2 100 6 VCC 3 0 V Ta 25 C I2 I1 2 I1 I2 2 100 Applied to both lDOL and lDOH 7 VCC 3 0 V IDO 85 C IDO 40 C 2 IDO 85 C IDO 40 C 2 100 Applied to both IDOL and IDOH 8 When Charge pump current is measured set LDS 0 T1 0 and T2 1 Parameter Symbol Condition Value Unit Min Typ Max Charge pump current rate IDOL IDOH IDOMT 5 VDO VCC 2 3 10 vs VDO IDOVD ...

Страница 8: ...is entered through Data pin On rising edge of Clock one bit of the serial data is transferred into the shift register On a rising edge of load enable signal the data stored in the shift register is transferred to one of latches depending upon the control bit data setting 1 Shift Register Configuration The programmable reference counter for the IF PLL The programmable reference counter for the RF P...

Страница 9: ...1 1 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 Divide ratio A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 Programmable Counter A1 to A7 Divide ratio setting bits for the swallow counter 0 to 127 N1 to N11 Divide ratio setting bits for the programmable counter 3 to 2 047 LDS LD fout signal select bit SWIF SWRF Divide ratio setting bit for the prescaler IF SWIF RF SW...

Страница 10: ...e ratio IF PLL 32 33 64 65 Prescaler divide ratio RF PLL 64 65 128 129 Current value CS 6 0 mA 1 1 5 mA 0 LD fout pin state LDS T1 T2 LD output 0 0 0 0 1 0 0 1 1 fout output frIF 1 0 0 frRF 1 1 0 fpIF 1 0 1 fpRF 1 1 1 Phase comparator input FCIF RF 1 FCIF RF 0 DoIF DoRF DoIF DoRF fr fp H L fr fp L H fr fp Z Z 1 2 1 VCO polarity FC 1 2 VCO polarity FC 0 Note Give attention to the polarity for using...

Страница 11: ...ion the phase comparator output signal is unpredictable This is because of the unknown relationship between the comparison frequency fp and the reference frequency fr which can cause a major change in the comparaor output resulting in a VCO frequency jump and an increase in lockup time To prevent a major VCO frequency jump the intermittent mode control circuit limits the magnitude of the error sig...

Страница 12: ...the Clock signal and transferred to a latch at the rise of the LE signal The following diagram shows the data input timing LSB MSB Clock Data LE t7 t1 t2 t3 t4 t5 t6 1st data 2nd data Control bit Invalid data Note LE should be L when the data is transferred into the shift register Parameter Min Typ Max Unit Parameter Min Typ Max Unit t1 20 ns t5 100 ns t2 20 ns t6 20 ns t3 30 ns t7 100 ns t4 30 ns...

Страница 13: ...nues to be so for three cycles or more tWU and tWL depend on OSCIN input frequency as follows tWU 2 fosc e g tWU 156 3 ns when fosc 12 8 MHz tWU 4 fosc e g tWL 312 5 ns when fosc 12 8 MHz IF PLL section RF PLL section LD output Locking state Power saving state Locking state Power saving state H Locking state Power saving state Unlocking state L Unlocking state Locking state Power saving state L Un...

Страница 14: ... VCCIF 1000 pF 0 1 µF 0 1 µF PSIF GNDIF finIF XfinIF GND OSCIN DoRF VCCRF PSRF GNDRF XfinRF finRF LE Data Clock S G S G S G 1000 pF 50 Ω 1000 pF 50 Ω 1000 pF 50 Ω 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 MB15F74UV 1000 pF VCCRF VCCIF Oscilloscope Controller divide ratio setting ...

Страница 15: ... 0 V VCC 3 6 V SPEC 0 10 20 30 40 50 Pfin RF dBm finRF MHz Ta 25 C Catalog guaranteed range 10 0 500 1000 1500 2000 2500 3000 VCC 2 7 V VCC 3 0 V VCC 3 6 V SPEC 0 10 20 30 40 50 Pfin IF dBm finIF MHz Ta 25 C Catalog guaranteed range RF PLL input sensitivity vs Input frequency IF PLL input sensitivity vs Input frequency ...

Страница 16: ...IN input sensitivity 10 0 20 40 80 100 140 160 VCC 2 7 V VCC 3 0 V VCC 3 6 V SPEC 0 10 20 30 40 50 60 120 Catalog guaranteed range Input sensitivity vs Input frequency Input frequency fOSC MHz Input sensitivity V OSC dBm ...

Страница 17: ...5 1 5 2 00 1 00 1 50 1 50 1 00 2 00 0 00 0 50 VCC 2 7 V Ta 25 C Charge pump output current I DO mA IDO VDO Charge pump output voltage VDO V IDO VDO Charge pump output current I DO mA Charge pump output voltage VDO V 8 00 8 00 1 0 3 0 0 0 2 0 0 5 2 5 1 5 6 00 4 00 4 00 6 00 2 00 0 00 2 00 VCC 2 7 V Ta 25 C ...

Страница 18: ... 100 000 000 MHz STOP 2 000 000 000 MHz 102 92 Ω 2 000 000 000 MHz 4 30 266 Ω 1 2 3 4 773 21 fF 37 563 Ω 109 96 Ω 2 GHz 26 125 Ω 71 227 Ω 3 GHz 22 848 Ω 54 025 Ω 3 5 GHz 1 2 3 START 2 000 000 000 MHz STOP 4 000 000 000 MHz 4 20 93 Ω 39 352 Ω 4 000 000 000 MHz 1 2 3 4 1 0111 pF finIF input impedance finRF input impedance ...

Страница 19: ...SCIN input impedance OSCIN input impedance 2 25 kΩ 2 2373 kΩ 10 MHz 881 62 Ω 1 8299 kΩ 20 MHz 448 75 Ω 1 353 kΩ 30 MHz 1 2 3 START 3 000 000 MHz STOP 40 000 000 MHz 4 278 69 Ω 1 0537 kΩ 40 000 000 MHz 1 2 3 4 3 7761 pF ...

Страница 20: ...mA mode fVCO 2113 6 MHz KV 50 MHz V fr 50 kHz fOSC 19 2 MHz LPF To VCO PLL Reference Leakage PLL Phase Noise ATTEN 10 dB RL 0 dBm CENTER 2 1136000 GHz RBW 1 0 kHz VBW 1 0 kHz SPAN 200 0 kHz SWP 500 ms MKR 80 83 dB 50 0 kHz VAVG 16 10 dB MKR 50 0 kHz 80 83 dB ATTEN 10 dB RL 0 dBm CENTER 2 11360000 GHz RBW 30 Hz VBW 30 Hz SPAN 10 00 kHz SWP 1 92 s MKR 65 34 dB Hz 1 00 kHz VAVG 16 10 dB MKR 1 00 kHz ...

Страница 21: ...9 99764 µs y 50 0009 MHz 500 µs 500 µs div 2 113604000 GHz 2 113600000 GHz 2 113596000 GHz 2 000 ms A Mkr x 400 00146 µs y 50 0013 MHz 4 500 ms 500 µs 500 µs div PLL Lock Up time 2113 6 MHz 2173 6 MHz within 1 kHz L ch H ch 1 47 ms PLL Lock Up time 2173 6 MHz 2113 6 MHz within 1 kHz H ch L ch 1 56 ms ...

Страница 22: ... LE Data Clock 1000 pF 1000 pF 1000 pF 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 MB15F74UV 1000 pF VCCRF Lock Detect OUTPUT VCO LPF VCO LPF OUTPUT TCXO VCCIF Controller divide ratio setting Note Clock Data LE The schmitt trigger circuit is provided insert a pull down or pull up registor to prevent oscillation when open circuit in the input ...

Страница 23: ...on 2 To protect against damage by electrostatic discharge note the following handling precautions Store and transport devices in conductive containers Use properly grounded workstations tools and equipment Turn off power before inserting or removing this device into or from a socket Protect leads with conductive sheet when transporting a board mounted device ORDERING INFORMATION Part number Packag...

Страница 24: ... 10 094 004 0 45 0 05 0 075 0 025 003 001 018 002 Stand off 0 45 018 TYP 2 31 090 1 90 075 REF 2 01 079 TYP TYP 0 45 018 1 35 053 2 28 090 A B C 15 10 6 6 1 15 10 0 28 0 06 011 002 0 36 0 06 014 002 C0 10 004 0 25 0 06 010 002 0 25 0 06 010 002 Details of B part Details of C part Details of A part 106 004 REF REF TYP INDEX AREA MIN 0 14 006 Mount height 011 002 0 28 0 06 014 002 0 36 0 06 0 90 035...

Страница 25: ...described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public a...

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