MB15F74UV
13
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PHASE COMPARATOR OUTPUT WAVEFORM
• LD Output Logic
Notes :
•
Phase error detection range
=
−
2
π
to
+
2
π
•
Pulses on Do
IF/RF
signals during locking state are output to prevent dead zone.
•
LD output becomes low when phase error is t
WU
or more.
•
LD output becomes high when phase error is t
WL
or less and continues to be so for three cycles or more.
•
t
WU
and t
WL
depend on OSC
IN
input frequency as follows.
t
WU
≥
2/fosc : e.g. t
WU
≥
156.3 ns when fosc
=
12.8 MHz
t
WU
≤
4/fosc : e.g. t
WL
≤
312.5 ns when fosc
=
12.8 MHz
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
fr
IF
/
RF
fp
IF
/
RF
LD
D
o
IF
/
RF
t
WU
t
WL
D
o
IF
/
RF
H
L
L
H
Z
Z
(FC bit
=
“1”)
(
FC bit
=
“0”
)
