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WATCHDOG TIMER V1.1

Chapter 5 Note on Using Watchdog Timer

MCU-AN-500013-E-11 – Page 12

5 Note on Using Watchdog Timer

Take account of the following points when using the watchdog timer.

Stopping the watchdog timer

Once activated, the watchdog timer cannot be stopped until a reset is generated.
If a HWWDT is select, it will resume operation after a reset.

Selecting the count clock

Software watchdog timer
The count clock switch bits (WDTC: CS1, CS0, CSP) can be rewritten only when the

watchdog control bits (WDTC: WTE3 to WTE0) are set to "0101B" upon the

activation of the watchdog timer. The count clock switch bits cannot be written by a

bit operation instruction. Moreover, the bit settings should not be changed once the

timer is activated.
In sub-clock mode, the timebase timer does not operate because the main clock

stops oscillating.
In order to operate the watchdog timer in sub-clock mode, it is necessary to select

the watch prescaler as the count clock beforehand and set "WDTC: CS1, CS0, CSP"

to "100

" or "110

" or "XX1

Hardware watchdog timer
The count clock is fixed at 2

CRL

Clearing the watchdog timer

Clearing the counter used for the count clock of the watchdog timer (timebase timer

or watch prescaler or sub-CR timer) also clears the counter of the watchdog timer.
The counter of the watchdog timer is cleared when entering the sleep mode, stop

mode or watch mode except in the case of selecting the hardware activation with the

hardware watchdog timer running in a standby mode.

Programming precaution

When creating a program in which the watchdog timer is cleared repeatedly in the

main loop, set the processing time of the main loop including the interrupt processing

time to the minimum watchdog timer interval time or shorter.

Hardware watchdog (with timer running in a standby mode)

The watchdog timer does not stop in stop mode, sleep mode, timebase timer mode

or watch mode. Therefore, the watchdog timer is not to be cleared by the CPU even

if the internal clock stops. (in stop mode, sleep mode, timebase timer mode or watch

mode).
Regularly release a standby mode and clear the watchdog timer. However, a

watchdog reset may be generated depending on the setting of the oscillation

stabilization wait time setting register after the CPU returns from stop mode in sub-

clock mode or sub-CR mode.
Take account of the setting of the sub-clock stabilization wait time when selecting the

sub-clock.

Содержание F2MC-8FX MB95200H/210H Series

Страница 1: ...Fujitsu Microelectronics Shanghai Co Ltd Application Note MCU AN 500013 E 11 F MC 8FX FAMILY 8 BIT MICROCONTROLLER MB95200H 210H SERIES WATCHDOG TIMER APPLICATION NOTE ...

Страница 2: ...will not be liable for infringement of copyright industrial property right or other rights of a third party caused by the use of information or drawings described in this manual 3 The contents of this manual may not be transferred or copied without the express permission of Fujitsu 4 The products contained in this manual are not intended for use with equipments which require extremely high reliabi...

Страница 3: ...Watchdog Timer Selection ID Register WDTH WDTL 6 2 4 NVR Non Volatile Register function 7 3 INTERVAL TIME 8 4 USAGE AND EXAMPLES 9 4 1 Functions and Operations of watchdog timer 9 4 2 Software watchdog timer 10 4 3 Hardware watchdog timer 11 5 NOTE ON USING WATCHDOG TIMER 12 6 ADDITIONAL INFORMATION 13 7 APPENDIX 14 7 1 List of Figures 14 7 2 List of Tables 15 7 3 Sample Code 16 7 3 1 Project Name...

Страница 4: ...1 Chapter 1 Introduction MCU AN 500013 E 11 Page 4 1 Introduction This application note describes how to use the watch dog timer The application note describes the functions of the watchdog timer and gives some examples ...

Страница 5: ... 3 The watchdog timer that is not cleared may be due to problems in the program which has entered into an infinite loop or Stack over run or other possible problems that caused the CPU to hang The watchdog timer has the following features Count clock selector Watchdog timer counter Reset control circuit is used to generate the reset signal when the WDT counter overflows Watchdog timer clear select...

Страница 6: ... 2 2 WDTC 2 3 2 Watchdog Timer Selection ID Register WDTH WDTL The two registers are used to select hardware or software watchdog timer Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FEBH WDTH WDTH7 WDTH6 WDTH5 WDTH4 WDTH 3 WDTH 2 WDTH 1 WDTH 0 xxxxxxxx 0FECH WDTL WDTL7 WDTL6 WDTL5 WDTL4 WDTL 3 WDTL 2 WDTL 1 WDTL 0 xxxxxxxx R WX R WX R WX R WX R WX R WX R WX R WX Figure 2 3 Watchdo...

Страница 7: ... note that either the SWWDT or HWWDT can work in the same time NVR is used to decide which one is working These 16 bits of WDTH and WDTL are loaded from the flash address FFBEH FFBFH after a reset The initial values are determined by the pre loaded values in the NVR flash area Write certain values to the address FFBEH and FFBFH to select watchdog timer s mode Table 2 1 shows watchdog timer selecti...

Страница 8: ...262 ms 524 ms Watch prescaler output sub clock 32 768KHz 100B SWWDT 214 FCL 500 ms 1 00 s 110B SWWDT 213 FCL 250 ms 500 ms Sub CR timer sub CR clock 50 200KHz XX1B SWWDT or HWWDT 1 216 FCRL 328 ms 2 62 s 1 CS 1 0 00B CSP 1B read only Table 3 1 Interval Times of Watchdog Timer The interval time varies depending on the timing of clearing the watchdog timer Figure 3 1 shows the correlation between th...

Страница 9: ...hould also be set at the same time 3 Once the watchdog timer is activated a reset is the only way to stop its operation Please clear watchdog counter in a specified intervals regularly depend on the setting of WDTC CS1 CS0 CSP Refer to Table 3 1 for detailed interval time Hardware watchdog 1 Write A597H WDT can be stopped in a standby mode or any other value WDT is enabled in every mode except tha...

Страница 10: ...r for operation with software mode main c startup asm Refer to Appendix Sample Code for project SWWDT Please note that once the watchdog timer is activated it cannot be stopped until a reset is generated THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES C Fujitsu Microelect...

Страница 11: ...CS0 CSP are fixed at 001 the interval time is fixed at 216 FCRL too The following example shows how to set watchdog timer for operating in hardware mode main c startup asm Refer to Appendix Sample Code for project HWWDT Please note that the hardware watchdog timer starts automatically after a reset and cannot stop its operation THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS FUJIT...

Страница 12: ...g timer Clearing the counter used for the count clock of the watchdog timer timebase timer or watch prescaler or sub CR timer also clears the counter of the watchdog timer The counter of the watchdog timer is cleared when entering the sleep mode stop mode or watch mode except in the case of selecting the hardware activation with the hardware watchdog timer running in a standby mode Programming pre...

Страница 13: ... Page 13 6 Additional Information For more information on FUJITSU MICROELECTRONICS Products please visit the following website at Simplified Chinese Version http www fujitsu com cn fmc services mcu mb95200 English Version http www fujitsu com cn fmc en services mcu mb95200 ...

Страница 14: ...14 7 Appendix 7 1 List of Figures Figure 2 1 Block Diagram of Watchdog Timer 5 Figure 2 2 WDTC 6 Figure 2 3 Watchdog Timer Selection ID Register WDTH WDTL 6 Figure 2 4 Retrieval of NVR during Reset 7 Figure 3 1 Clearing Timing and Interval Time of Watchdog Timer 8 ...

Страница 15: ...WATCHDOG TIMER V1 1 Chapter 7 Appendix MCU AN 500013 E 11 Page 15 7 2 List of Tables Table 2 1 Watchdog Timer Selection ID 7 Table 3 1 Interval Times of Watchdog Timer 8 ...

Страница 16: ...main c include mb95200 h name Delay function delay function void Delay unsigned int i while i asm tNOP name InitWDT function initial watchdog timer void InitCompTimer void WDTC 0x05 set count clock is 221 FCH start WDT counter name main function main loop void main void PDR0_P05 0 initial value DDR0_P05 1 set P05 as output InitWDT ...

Страница 17: ...R0_P05 show program is normal run Delay 500 WDTC 0x05 clear WDT timer within a certain amount of time startup asm variable define declaration define HWD_DISABLE if define this Hard Watchdog will disable Hard Watchdog ifdef HWD_DISABLE SECTION WDT CONST LOCATE H FFBE DATA W 0xA596 endif ...

Страница 18: ...ally after a reset and cannot be stopped The internal time is fixed to 216 FCRL name Delay function delay function void Delay unsigned int i while i asm tNOP name main function main loop void main void PDR0_P05 0 initial value DDR0_P05 1 set P05 as output while 1 PDR0_P05 PDR0_P05 show program is normal run Delay 500 WDTC 0x05 clear WDT timer within a certain amount of time ...

Страница 19: ...ter 7 Appendix MCU AN 500013 E 11 Page 19 startup asm variable define declaration define HWD_DISABLE if define this Hard Watchdog will disable Hard Watchdog ifdef HWD_DISABLE SECTION WDT CONST LOCATE H FFBE DATA W 0xA596 endif ...

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