FujiFilm FINEPIX A400, Руководство по обслуживанию

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3. Schematics
FinePix A400 Service Manual
3-3. Functions of Primary Blocks
3-3-1. Technical Outline
„ Equipped with a 1/2.5-inch Super CCD HR (with 4.1 effective megapixels) and a Fujinon 3x optical zoom lens.
„ Features a new image signal processing LSI chip, called the XCS2R_IC (IC204, CSP_IC), built into the MAIN PWB
ASSY. This CPU incorporates the standard peripheral I/O functions as well as the peripheral functions required for still
image processing into a single chip. Standard peripheral I/O consists of the interrupt controller, DMA controller, clock
controller, SDRAM controller, block selection controller, serial I/O, multifunction timer, monitoring timer, programmable I/O
ports, USB 2.0 (Full Speed), microprocessor ADC, microprocessor DAC, image processing circuit, JPEG compression/
expansion circuit, display control circuit, still image processing and card interface circuit.
„ In the white balance procedure, an algorithm has been installed that provides an estimation of the light source used for
shooting based on the brightness and light source color detected when the shot was taken, and a white balance (WB)
compensation function based on that estimation. The new algorithm is designed to prevent “hunting” due to field-of-view
slippage by providing more accurate brightness and color detection, and to allow the installation of a powerful algorithm
for distinguishing between the light source and the original subject colors.
„
Flash brightness is adjusted using the CCD-TTL method in which the flash brightness is calculated from the CCD
feedback data generated by the pre-flash.
Explanation of the imaging circuit functions
„ Analog video signals output from the CCD (1/2.5-inch with 4.1 effective megapixels) undergo pseudo-color correction
processing, adaptive interpolation processing, amplification and signal mixing in the BCS-R_IC (IC104; CSP_IC). The
converted digital signals are then sent to the single-chip image signal processing LSI chip, known as XCS2R_IC (IC204,
CSP_IC).
„ Input data from the CCD
* The 10-bit digital image data (corresponding to 1H) sent from the imaging circuit (BCS-R) is sent to XCS2R_IC, buffered
in the chip’s IBFC and replaced by 16-bit (96 MHz) data. The replaced 16-bit (96 MHz) image data is then stored in the
XCS2R_IC [SDRAM] via the XCS2R_IC [I/O BUFFER]. The image data for each frame is temporarily stored in the
XCS2R_IC [SDRAM].
* At the same time, the AE for [AUTO] is calculated using the 10-bit image data input to XCS2R_IC and the data required
for AE, AWB and AF is sent to the XCS2R_IC [SDRAM]. In the XCS2R_IC [SDRAM], the data is sent serially to AFE_CS
to obtain the correct AE, AWB and AF.
„
Recording onto an xD-Picture card
The image data stored in SDRAM is converted to 16-bit (96-MHz) data by [IBFC] in XCS2R_IC one line at a time and
then sent to [YC PRO]. In [IBFC], the 32-bit Y and C signals are each converted to 8-bit Y, Y, Cb and Cr signals and sent
to the XCS2R_IC [SDRAM]. The image data stored in the XCS2R_IC [SDRAM] is compressed using [JPEG] in
XCS2R_IC and then recorded sequentially onto the xD-Picture card via [MEDIA] in XCS2R_IC.
„
Playing back images from an xD-Picture card
The compressed image data from the xD-Picture card is sent to XCS2R_IC and stored in the XCS2R_IC [SDRAM] via
[MEDIA]. The compressed image data stored in the XCS2R_IC [SDRAM] is expanded using [JPEG] and again stored in
the XCS2R_IC [SDRAM]. The expanded image data is sent to [YC PRO] via [IBFC]. In [YC PRO], gain control and
aperture processing is applied for the brightness signals and color difference signals, after which the data is again stored
in the XCS2R_IC [SDRAM]. The image data is then displayed via [ENCD] and [D/A].
„ In movie shooting mode
The 10-bit digital image data output from the imaging unit is converted to 8-bit Y and C signals by the XCS2R_IC [YC
PRO] and sent to the XCS2R_IC [SDRAM]. The image data is compressed using [JPEG] in XCS2R_IC and again stored
in the XCS2R_IC [SDRAM]. The compressed data is then recorded sequentially onto the xD-Picture card via [MEDIA] in
XCS2R_IC.
„ The imaging system adjustment data is stored in FLASH_ROM (IC201).
Explanation of the LCD controller functions
„ The R, G and B signals processed in the XCS2R_IC image signal processor are output to the LCD panel via [LCD
CONST].
LCD Unit
„ The LCD monitor (1.8-inch 77,000 pixels) used in the camera uses a low-temperature polysilicon TFT color LCD screen.
Power Supply Section
„ Power supply circuits constructed in the core of the HPS_IC (IC313) create the following power supplies, which are
supplied to each block.
CAM3.3V
[IC104 (BCS-R), IC103 (V_Drv)]
15V [IC103 (V_Drv), IC11 (CCD)]
5V [IC103 (V_Drv)]
-8V [IC103 (V_Drv), IC11 (CCD)]
3.3V_SYS [IC701 (Motor_Drv), IC204 (XCS2R)]
3.3V_ RUN [IC701 (Motor_Drv)]
1.5V_RUN [IC204 (XCS2R)]
8.5V_LCD [LCD (CN501)]
3VA_OUT [LCD (CN501), IC401 (Video Driver)]
VUNREG [STRB (CN901)]