FT8U2XXAM
High Speed USB Controllers for serial and FIFO applications
Future Technology Devices Intl. AN232-08 Rev 1.00 Page
4
2. The Self Powered Schematic with extended RESET# period.
Please refer to the “Bus powered schematic with extended reset period” notes ( above )
for an explanation of the issues relating extending the reset period.
In this example, RESET# is coming from a source, where it is longer than 10 milliseconds
such as a reset generator i.c or a MPU IO pin etc. As a result, the USB D+ line cannot be
pulled high immediately on powering up the host, but has to wait until the extended reset
period is over. Again, we use the familiar series transistor circuit on USB D+ but this time
the transistor has to be turned off under two conditions –
1. USB Power from the host or hub is off ( see above for why )
2. The device is still being held in reset.
The solution outlined here uses a CMOS AND gate to achieve the desired function,
though it is also possible to achieve the same function using all discrete components also.
Also note that the 100k pull-up on RCCLK is connected to RESET# and not to VCC. The
reason for this has been explained in the Bus Powered section.
RESET#
0.1uF
RCCLK
1.5K
USBDP (D+)
3v3OUT
Connections for RESET#, RCCLK and USBDP in an extended RESET# bus powered mode
2N3904
USBVCC
Transistor is used to
prevent supplying
current upstream
when host PC is
powered off. It is also
used to prevent this
device being seen until
the reset period is
over.
GND
100K
Long RESET#
AND Gate
100K
20K
