Model VM32PAFF
32 Channel VME Module
Programmable Amplifier
Programming
With Fixed Frequency Filter
17
1784 Chessie Lane., Ottawa, IL 61350
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Tel: 800/252-7074, 815/434-7800
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FAX:815/434-8176
e-mail: [email protected]
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Web Address: http://www.freqdev.com
Programming Procedure
To write gain data to a channel, the user first reads the CHADR (Base A 0) and tests its BUSY bit
to see if the serial interface is busy. If BUSY is set, the user can go on to other things and come back to
the board later, or the user can poll CHADR, waiting for BUSY to clear. Once BUSY is found clear the user
writes the desired channel address to CHADR. The user must also make sure to write ‘0’ to the BUSY bit.
Once the desired channel has been selected, the user then sets that channel’s gain by writing the desired
gain data to DATA (Base A 2). The VM32PAFF automatically sets the BUSY bit in the CHADR
register to indicate that the serial bus is transferring data. The BUSY bit is automatically cleared once the
transfer is complete. The serial channel will be busy for approximately 4 microseconds.
To read a channel's gain setting, the user first tests the BUSY bit to see if the serial interface is busy by
reading CHADR’s BUSY bit. If BUSY is set, the user can go on to other things and come back to the board
later, or the user can poll CHADR, waiting for BUSY to clear. Once BUSY is found clear, the user writes
the desired channel address to CHADR, making sure to write a '1' to the BUSY bit. The serial interface
accesses gain data from the selected channel and clears the BUSY bit in CHADR when the requested data
is available in DATA. The requested data is available in DATA approximately 4 microseconds after writing
to CHADR.
Please note, when a flag can be controlled by two or more systems, instructions that generate
read/modify/write cycles (or read followed by write cycles) should be avoided while testing the state of the
BUSY bit. The safest way to test BUSY is to read CHADR into a local register and then test the state of
the BUSY bit in the registered copy.
In addition to VM32PAFF register map,
Figure 5-1
also defines the read/write function of each bit. Notice
that registers may be accessed as words or as bytes.
Programming Considerations
There are some considerations that the user must take into account for when trying to program the
VM32PAFF.
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Attempting to access the VM32PAFF board in other than A16 address space will cause a bus
timeout.
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Attempting long word access or unaligned transfers will cause the board to respond to the bus cycle
with a bus error (BERR).
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Changing the channel address while BUSY is set results in erroneous data during a data read
operation and will corrupt the settings of two or more channels during a data write operation.
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VM32PAFF hardware prevents changing of the channel selection while BUSY.
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Writing to the Data Register or the Reset Register while BUSY is set is inhibited in hardware.
None of these events are flagged by the board, so it is important to use the BUSY interlock before writing
to any register.
