Freetech P6F127, Руководство пользователя

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Introduction
Chipset 11
2.7. Chipset
The P6F127 supports the VIA 82C694X Apollo Pro-133A chipset.
The chipset comes in pairs—the North Bridge chip and the South
Bridge chip.
North Bridge
•
CPU interface controller (66/100/133 MHz FSB)
•
AGP interface controller (AGP 1x/2x/4x)
•
Integrated DRAM controller
(Synchronous 66/100/133 MHz SDRAM)
•
Fully synchronous PCI 2.2 bus interface
•
Data buffering:
♦
CPU-to-AGP
♦
CPU-to-DRAM
♦
CPU-to-PCI
♦
AGP-to-DRAM
♦
AGP-to-PCI
♦
PCI-to-AGP
♦
PCI-to-DRAM
South Bridge
•
Interface between the PCI and ISA buses
•
Power Management Logic
•
USB controller
•
EIDE controller (ATA33/66/100)
•
Seven DMA channels
•
One timer/counter
•
Two 8-channel interrupt controllers
•
NMI logic and SMI interrupt logic
•
PCI/ ISA bus arbitrator
•
SMBus interface
•
Power management Logic
•
Realtime clock (RTC)
•
ACPI controller
This concludes Chapter 2. Chapter 3 covers hardware installation.