Freescale Semiconductor MC9S08PA32, Технические данные инструкция

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Table 5. Control timing (continued)
Num C Rating Symbol Min Typical
1
Max Unit
7 D IRQ pulse width Asynchronous
path
2
t
ILIH
100 — — ns
D Synchronous path t
IHIL
1.5 × t
cyc
— — ns
8 D Keyboard interrupt pulse
width
Asynchronous
path
2
t
ILIH
100 — — ns
D Synchronous path t
IHIL
1.5 × t
cyc
— — ns
9 C Port rise and fall time -
Normal drive strength
(HDRVE_PTXx = 0) (load
= 50 pF)
— t
Rise
— 10.2 — ns
C t
Fall
— 9.5 — ns
C Port rise and fall time -
Extreme high drive
strength (HDRVE_PTXx =
1) (load = 50 pF)
4
— t
Rise
— 5.4 — ns
C t
Fall
— 4.6 — ns
1. Typical values are based on characterization data at V
DD
= 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t
MSH
after
V
DD
rises above V
LVD
.
4. Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range -40 °C to 105 °C.






 
t
extrst
RESET PIN
Figure 5. Reset timing
t
IHIL
KBIPx
t
ILIH
IRQ/KBIPx
Figure 6. IRQ/KBIPx timing
5.2.2 Debug trace timing specifications
Table 6. Debug trace operating behaviors
Symbol Description Min. Max. Unit
t
cyc
Clock period Frequency dependent MHz
t
wl
Low pulse width 2 — ns
t
wh
High pulse width 2 — ns
t
r
Clock and data rise time — 3 ns
t
f
Clock and data fall time — 3 ns
Table continues on the next page...
Switching specifications
MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.
14 Freescale Semiconductor, Inc.