Hardware Description
Designer Reference Manual
DRM047 — Rev 0
30
Hardware Description
MOTOROLA
Figure 3-4. LIN Stepper Controller (Slave) Board Schematic
The 908E625 schematics with the LIN Stepper Controller functional
blocks is in
. The he functional blocks are described below.
3.2.1 MCU and Power Die with SPI
MCU 908EY16 chip and Power Die chip (Cairone) forms the 908E625
device in one package. These two chips are connected with SPI signals
and some other signals. So the control of the Power Die (like
Half-bridges control) is provided with SPI communication. The SPI
communication pins MISC, MOS, SPCLK are connected inside of the
908E625 package (see
).
VDD
GND
IRQ_RQ
SensorA2
PTB7/AD7/TBCH1
1
PTB6/AD6/TBCH0
2
PTC4/OSC1
3
PTC3/OSC2
4
IRQB_SMOS
18
RSTB_SMOS
17
FGEN
15
PTD0/TACH0/BEMF
12
PTB1/AD1
11
RSTB_MCU
10
IRQB_MCU/FLSEPGMN
9
VSUP
31
GND
30
HB3
29
HS
28
VSUP
27
HB2
26
GND
25
VSUP
24
H2
36
H1
37
VDD
38
PA1
39
PTA1/KBD1
53
PTA0/KBD0
54
HB1
23
EVDD
46
VDDA
47
PTE1/RxD
42
BEMF
16
VREFL
43
VSSA
44
EVSS
45
PTA2/KBD2
52
FLSVPP
51
PTA3/KBD3
50
PTA4/KBD4
49
H3
35
HVDD
34
NC
33
HB4
32
PTB3/AD3
8
PTB4/AD4
7
PTB5/AD5
6
PTC2/MCLK
5
LIN
20
SSB
19
NC
22
NC
21
PTD1/TACH1
13
RxD
41
PTA6/SSB
14
VSS
40
VREFH
48
U1
PM908E625ACDWB
VSS
VDD_A
VDD_A
VSS
1
2
JP1
HDR 2X1
VDD
VDD
VSUP
GC1
CON
SensorA1
GC2
CON
+
C2
330u/35
VSUP_LIN
C1
100p
BEMF
IRQ_RQ
BEMF
VSS_A
RST
GC3
CON
C4
100n
FGEN
FGEN
SSB
SSB
C3
100n
VSS_A
PTC4/OSC
IRQ_RQ
IRQ_IN
1
2
3
4
J1
POWER_HDR4
GND
1
J5
HDR 1
10
7
6
5
4
3
2
1
9
8
J2
CON/10MICROMATCH
PTB4/AD4
PTB3/AD3
VDD
PTA1/KBD1
VSS
+
C5
2u2/10
PTA0/KBD0
RST
VDD_A
R4
1k5
VDD_A
1
2
3
4
5
6
J3
HDR 6X1
IRQ_IN
D1
LED_YELL
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Freescale Semiconductor, Inc.
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