Freescale Semiconductor LS1043ARDB, Быстрый старт

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5.1 SW3 configuration
The figure below shows the SW3 switch on the LS1043ARDB.
CLKGEN_FS0
1
2
3
4
5
6
7
8
CLKGEN_FS1
UART_SEL
SD1REFCLK_SEL
EVDD_SEL
OPENSDA_EN
TDMCLK_SD/USB
SDHC_SPICS_SEL
ON '1'
Figure 4. SW3 switch
The table below describes the SW3 configuration.
Table 2. SW3 configuration
Switch Name Description ON (1) / OFF (0) setting
SW3[1] CLKGEN_FS0 SYSCLK frequency select
• 00: 66.66 MHz
• 01: 80 MHz
• 10: 100 MHz (default value)
• 11: 83 MHz
1
SW3[2] CLKGEN_FS1 0
SW3[3] UART_SEL UART1 output select
• 0: RJ45, J4 lower one
• 1: CMSISDAP, mini-USB port (default
value)
1
SW3[4] SD1REFCLK_SEL SD1 REFCLK select
• 0: 100 MHz (default value for the
LS1021A interposer)
• 1: 156.25 MHz (default value for the
LS1043A processor)
1
SW3[5] EVDD_SEL EVDD voltage select
• 0: 3.3 V (default value)
• 1: 1.8 V
0
Table continues on the next page...
Switch configurations
QorIQ LS1043A Reference Design Board Quick Start, Rev. 1, 11/2015
Freescale Semiconductor, Inc. 5