Freescale Semiconductor e200z3, Справочное руководство

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External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 7-19
Table 7-13 describes the processor reservation signals associated with lwarx and stwcx..
Table 7-14 describes miscellaneous processor signals.
Table 7-12. Descriptions of Timer Facility Signals
Signal I/O Signal Description
p_tbdisabl
e
I Timer disable. Used to disable the internal time base and decrementer counters. Used to freeze the state of
the time base and decrementer during low power or debug operation.
State
Meaning
Asserted—Time base and decrementer updates are frozen.
Negated—Time base and decrementer updates are unaffected.
Timing Not internally synchronized by the core; must meet setup and hold time constraints relative to
m_clk when the core clock is running, as well as to p_tbclk when selected as an alternate time
base clock source.
p_tbclk I Timer external clock. Used as an alternate clock source for the time base and decrementer counters.
Selection of this clock is made using HID0[SEL_TBCLK] (see
Section 2.13.1, “Hardware
Implementation-Dependent Register 0 (HID0)” ).
Timing Must be synchronous to the m_clk input and cannot exceed 50% of the m_clk frequency. Must be
driven such that it changes state on the falling edge of m_clk.
p_tbint O Timer interrupt status. Indicates whether an internal timer facility unit is requesting an interrupt
(TSR[WIS]=1 and TCR[WIE]=1, or TSR[DIS]=1 and TCR[DIE]=1, or TSR[FIS]=1 and TCR[FIE]=1). May be
used to exit low power operation or for other system purposes.
State
Meaning
Asserted—An internal timer facility unit is generating an interrupt request.
Negated—An internal timer facility unit is not generating an interrupt request.
Table 7-13. Descriptions of Processor Reservation Signals
Signal I/O Signal Description
p_rsrv O CPU reservation status. Indicates whether a reservation was established by the execution of an lwarx .
State
Meaning
Asserted—A reservation was established by successful execution of an lwarx . Remains
asserted until the reservation is cleared.
Negated—No reservation is in effect.
Timing Assertion—Remains asserted until the reservation is cleared.
p_rsrv_cl
r
I CPU reservation clear. Used to clear a reservation. External logic may use this signal to implement reservation
management policies outside the scope of the CPU.
p_xfail_b indicates success/failure of an stwcx. as part
of bus transfer termination using the XFAIL p_hresp[2:0] encoding.
State
Meaning
Asserted—Signals that a reservation should be cleared. Asserted independently of any bus
transfer.
Timing Assertion—Asserted independently of any bus transfer.
Table 7-14. Descriptions of Miscellaneous Processor Signals
Signal I/O Signal Description
p_cpuid[0:7]
I CPU ID. Reflected in the PIR. See Section 2.4.2, “Processor ID Register (PIR).”
Timing Intended to remain in a static condition and are not internally synchronized.
p_pid0[0:7]
O PID0 outputs. Reflected to PID0[56–63]. See Section 2.16.5, “Process ID Register (PID0).”