Freescale Semiconductor e200z3, Справочное руководство

Страница: 117 / 442

Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 2-69
The MAS6 register is shown in Figure 2-52 .
MAS6 fields are defined in Table 2-37 .
2.16.5 Process ID Register (PID0)
The process ID register, PID0, is shown in Figure 2-53 . The Book E architecture requires that a process
ID (PID) value be associated with each effective address (instruction or data) generated by the processor.
Book E defines one PID register that maintains the value of the PID for the current process. The number
of PIDs implemented is indicated by the value of MMUCFG[NPIDS]. (The e200z3 defines no additional
PID registers.) PID values are used to construct virtual addresses for accessing memory.
2.17 Support for Fast Context Switching
To provide real-time capabilities for embedded systems, future versions of the e200z3 core will include
optional hardware support for fast context switching. The initial version of the e200z3 does not implement
additional register contexts.
32 39 40 47 48 62 63
Field — SPID — SAS
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 630
Figure 2-52. MMU Assist Register 6 (MAS6))
Table 2-37. MAS6—TLB Search Context Register 0
Bits Name Description
32–39 — Reserved, should be cleared.
40–47 SPID PID value for searches
48–62 — Reserved, should be cleared.
63 SAS AS value for searches
32 55 56 63
Field — Process ID
Reset All zeros
R/W R/W
SPR SPR 48
Figure 2-53. Process ID Register (PID0)