
56F8037EVM User Manual, Rev. 0
1-2
Freescale Semiconductor
Preliminary
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8037EVM is flexible enough to allow a user to fully exploit the 56F8037's
features to optimize the performance of his product, as shown in
Figure 1-1
.
56F8037
RESET
JTAG/EOnCE
SPI
SCI
Timer A
PWM
+3.3V & GND
+3.3VA & AGND
Daughter Card
Connector
IRQ Pushbuttons
JTAG
Connector
USB
Type-B
SCI to USB
Bridge
Power Supply
+3.3V &+3.3VA
RESET Pushbutton
Debug LEDs
ADCA
ADCB
Figure 1-1. Block Diagram of the 56F8037EVM
1.2 56F8037EVM Connections
There are several power connection arrangements supported by the 56F8037EVM. Power can be
provided to the 56F8037EVM by using a USB connector, P2, attached to a PC or USB hub.
Power can be provided to the 56F8037EVM by an ex9.0V DC power supply using the
2.1mm power jack, P1, or via the Daughter Card connector, P3. However, the debug interconnect
is always the same using the JTAG connector, J1.
1.2.1 USB Power Connection
An interconnection diagram is shown in
Figure 1-2
for connecting the JTAG Debug and USB
between a PC and the 56F8037EVM.
Содержание 56F8037
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