ERROR CONTROL CRC
Error control is implemented with a CRC following each data packet. The CRC is
radix to 7 bits giving a value between 0 and 127. The CRC is simply the addition of
all packets data values including the address and start byte (0xFF). For example, a
command to run lamp 0 focus motor would be 0xFF, 0x90, 0x0B. The addition of
these values give 0x19A. The CRC would therefore be this value radix to 7 bits to
give a value of 0x1A. This value is sent as the last byte of the packet.
DATA TIMING
Data packets can be sent up to 10 times per second. Each packet starts with value
0xFF. The remaining bytes should follow immediately. The whole packet must be
received within 30mS. A packet lasting longer than 30mS will be rejected.
There is no minimum packet send rate.
When the FBUS interface receives the DATA_REQUEST_LAMP_STATUS
command there is a 2-30mS delay after which the FBUS interface switches to
transmit and outputs 13 data bytes in direct succession. After the last byte has been
sent the interface will switch back to receive.