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Chapter 3 BIOS Description
CAS# Latency (Tcl)
This option controls the CAS latency, which determines the timing delay (in
clock cycles) before SDRAM starts a read command after receiving it.
RAS# to CAS# delay (Trcd)
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS
(row address strobe) to CAS (column address strobe). The less the clock cycles,
the faster the DRAM performance.
Min RAS# active time (Tras)
This setting determines the time RAS takes to read from and write to a memory
cell.
Row Precharge Time (Trp)
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate
its charge before DRAM refresh, refreshing may be incomplete and DRAM may
fail to retain data. This item applies only when synchronous DRAM is installed
in the system.
DRAM Configuration Menu
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