Force Computers SYS68K/CPU-40, Руководство пользователя

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS
3-2
3.2 The Shared RAM
On this CPU board the shared RAM is placed on a module to allow the adaptation of DRAM or SRAM to
the base board.
All signals which are needed to control the shared RAM are available on the RAM module connector.
Therefore RAM devices with different access times can also be used on this CPU board to take advantage
of the 68040 with higher frequency if it becomes available.
3.2.1 General Operation
The Shared RAM is accessible from the 68040 and from the VMEbus. The access address for the 68040
starts at $00000000. The access address for the VMEbus is software programmable in 4 Kbyte steps. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only be read.
If an access from the VMEbus takes place the onboard logic requests the local bus mastership from the
local arbiter via the FGA-002 Gate Array. After the arbiter has granted local bus mastership to the FGA-002
Gate Array, the access cycle is executed. A read cycle is terminated by latching all data from the memory;
a write cycle is ended by storing the data in the memory cells. Both read and write cycles are terminated
on the local bus side and the FGA-002 Gate Array immediately releases bus mastership to the CPU while
completing the fully asynchronous VMEbus access cycle.
3.2.2 Shared RAM Information
The RAM module connector holds several signals which are software readable and inform the user
concerning RAM type and functionality.
These pins are readable via the PI/T2 device which is installed on the CPU board. For base address and
register address information please refer to the chapter 3.9.9
Address Map of the PI/T2 Registers for
further information.