Force Computers SYS68K/CPU-40, Руководство пользователя

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SECTION 3 HARDWARE USER'S MANUAL
5-1
5. THE CPU BOARD INTERRUPT STRUCTURE
All interrupts on the CPU board are handled via the FGA-002 or the hardware which is controlling the
FLXibus.
The interrupts of the FLXibus and the interrupts handled by the FGA-002 are daisy chained. If an interrupt
occurs on the FLXibus with the same priority as an interrupt occurring through the FGA-002, the priority is
as follows:
Priority of the Onboard Interrupts
Highest Priority
FLXibus
FGA-002
Lowest Priority
The interrupts which are caused by the EAGLE module are described in Section 6, EAGLE Module.
Interrupts handled by the FGA-002 are described in the following paragraphs.
The Gate Array installed on the CPU board handles all local and VMEbus interrupts. Each interrupt request
from the local bus through the two DUSCCs, RTC, the two timers, as well as the Gate Array specific
interrupt requests, are combined with seven VMEbus interrupt requests.
Each IRQ source including VMEbus IRQs can be programmed to interrupt the CPU on an individual
programmable level (1 to 7).
The Gate Array supports the vector, or initiates an interrupt vector fetch from the I/O device or from the
VMEbus.
In addition to local interrupts, the ACFAIL and SYSFAIL signals can be used to interrupt the CPU on a
software programmable level.
Gate Array supplied interrupt vectors have basic vector and fixed increments for each source. The basic
vector is software programmable.
For a complete description of interrupt handling, please refer to the FGA-002 Users Manual.