Force Computers SPARC CPU-54, Справочное руководство

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SYSFAIL and ACFAIL Interrupt Control Register Maps and Registers
5 - 12 SPARC/CPU-54
SYSFAIL and ACFAIL Interrupt Control Register
Note: SYSFAIL/ACFAIL are rising edge sensitive.
Table 35: SYSFAIL and ACFAIL Interrupt Control Register
Address: F160000A
16
Bit Signal Description Access
0 IE_SYSF Enables SYSFAIL interrupt.
0: SYSFAIL interrupt enabled
1: SYSFAIL interrupt disabled r/w
1 IP_SYSF Reflects if SYSFAIL interrupt is pending.
0: No SYSFAIL interrupt is pending.
1: SYSFAIL interrupt is pending. r/w
2 IE_ACFAIL Enables ACFAIL interrupt.
0: ACFAIL interrupt disabled
1: ACFAIL interrupt enabled r/w
3 IP_ACFAIL Reflects if ACFAIL interrupt is pending due to a
low to high transition of signal SYSFAIL.
0: No ACFAIL interrupt pending
1: ACFAIL interrupt pending r/w
4...7 Reserved Reserved r