Force Computers SPARC CPU-54, Справочное руководство

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Maps and Registers Control and Status Register
SPARC/CPU-54 5 - 9
Control and Status Register
The temperature sensors may be programmed in such a way that either
the O.S. output is operating in the Comparator Mode or the Interrupt
Mode.
In the comparator mode the O.S output is cleared (0) when the current
temperature exceeds an upper temperature limit (T
OS
); and the O.S. out-
put is set (1) only when the current temperature falls below a lower lim-
it (T
HYST
).
In the interrupt mode the O.S output is cleared (0) whenever the current
temperature exceeds an upper temperature limit (T
OS
), or falls below a
lower limit (T
HYST
). The O.S. output is set (1) only upon reading one of
the temperature sensor’s internal registers across the I
2
C Bus.
Table 32: Control and Status Register
Address: F1600005
16
Bit Signal Description Access
0 SW_PLCC_
TSOP Simulates SW6-2 by software.
0: Bit is cleared after reset.
1: Bit is set by Software, then BOOT-PLCC
device is switched off and TSOP BOOT Flash
device is selected in corresponding BOOT mem-
ory area. r/w
1 PS/2_KBD_
MSE Reflects whether there is a PS/2 adapter cable
plugged to front panel keyboard/mouse con-
nector or not.
0: No PS/2 adapter cable
1: PS/2 adapter cable plugged to front panel
keyboard/mouse connector. r
2 IS_TEMP1 Reflects state of output signal O.S. of first LM75
digital temperature sensor.
0: Bit is cleared, state of signal is low.
1: State of temperature sensor’s output signal is
high. r
3 IS_TEMP2 Reflects state of output signal O.S. of second
LM75 digital temperature sensor.
0: Bit is cleared, state of signal is low.
1: State of signal is high. r
4...7 Reserved Reserved r