Force Computers SPARC CPU-54, Справочное руководство

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Control Register Maps and Registers
5 - 8 SPARC/CPU-54
Control Register
The following register serves to control and monitor various conditions
of the SPARC/CPU-54.
Table 31:
Control Register
Address: F1600004
16
Bit Signal Description Access
0 Reserved Reserved r
1 Reserved Reserved r
2 EJECT_FD Ejects floppy disk in floppy disk drive.
0 (default): Bit is cleared
1: Bit is set, floppy disk ejected. r/w
3 RESET_STAT_
CLR Clears status bits in Reset Status register after
reset occurred and software has determined rea-
son for reset.
0: Bit is cleared.
1: Bit is set (1), all status bits are cleared. r/w
4...7 Reserved Reserved r