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L850-GL Hardware User Manual Page 19 of 54
Pin Pin Name
I/O Reset Value
Pin Description
Type
46
SYSCLK
O
PD
26M clock output
1.8V
47
PERn0
I
PCIe RX Differential signals
Negative
48
TX_BLANKING
O
PD
PA Blanking Timer, Reserved
CMOS 1.8V
49
PERp0
I
PCIe RX Differential signals Positive
50
PERST#
I
T
Asserted to reset module PCIe interface
default. If module went into core dump, it
will reset whole module, not only PCIe
interface.
Active low, internal pull up(10KΩ)
CMOS 3.3V
51
GND
GND
Power Supply
52
CLKREQ#
O
T
Asserted by device to request a PCIe
reference clock be available (active
clock state) in order to transmit data. It
also used by L1 PM Sub states
mechanism, asserted by either host or
device to initiate an L1 exit.
Active low, internal pull up(10KΩ)
CMOS 3.3V
53
REFCLKN
I
PCIe Reference Clock signal
Negative
54
PEWAKE#
O
L
Asserted to wake up system and
reactivate PCIe link from L2 to L0, it
depends on system
whether supports wake up functionality.
Active low, open drain output and should
add external pull up on platform
CMOS 3.3V
55
REFCLKP
I
PCIe Reference Clock signal
Positive
56
RFE_RFFE2_
SCLK
O
MIPI Interface Tunable ANT,
RFFE2 clock, Open Drain output
CMOS
3.3/1.8V
57
GND
GND
Power Supply
58
RFE_RFFE2_
SDATA
O
MIPI Interface Tunable ANT,
RFFE2 data, Open Drain output
CMOS
3.3/1.8V
59
ANTCTL0
O
Tunable ANT CTRL0
CMOS 1.8V
60
COEX3
I/O
PD
Wireless Coexistence between WWAN
and WiFi/BT modules, based on BT-SIG
CMOS 1.8V