Fastwel CPB902, Руководство пользователя

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Functional Description CPB902
C P B 9 0 2 U s e r M a n u a l
31
© 2 0 0 8 F a s t w e l v . 1 . 5 b E
Port
(hex)
Bit Read Write Value Comment
0
0 yes yes
1
EN_232_COM3 line status
0
1 yes yes
1
EN_232_COM4 line status
0
2 yes yes
1
EN_232_COM5 line status
0
3 yes yes
1
EN_232_COM6 line status
4 yes no 0 –
5 yes no 0 –
6 yes no 0 –
31D*
7 yes no 0 –
0
0 yes yes
1
0
1 yes yes
1
0
2 yes yes
1
0
3 yes yes
1
0
4 yes yes
1
0
5 yes yes
1
0
6 yes yes
1
0
31E
7 yes yes
1
FPGA registers (marked with *) access control.
To allow access to FPGA registers it is necessary
to write 55h to the port.
After reset contains FFh
0
0 yes no
1
COM3 port interrupt request line status
0
1 yes no
1
COM4 port interrupt request line status
0
2 yes no
1
COM5 port interrupt request line status
0
3 yes no
1
COM6 port interrupt request line status
0 UART reference frequency is 1.8432 MHz
4 yes yes
1 UART reference frequency is 14.7456 MHz
00 UART base address – 100h, ID register address – 142h
01 UART base address – 180h, ID register address – 1
С
2h
10 UART base address – 200h, ID register address – 242h
6,5
yes yes
11 UART base address – 280h, ID register address – 2
С
2h
0 Direct interrupt lines status output
142,
1C2,
242,
2C2
(ID
regis-
ter)
7 yes yes
1 Inverted interrupt lines status output
Notes: Gray color marks values after reset
The ports marked with "*" are not available for read/write after hardware reset (see port 31E , Table 4.3)