Functional Description
CPB902
C P B 9 0 2 U s e r M a n u a l
43
© 2 0 0 8 F a s t w e l v . 1 . 5 b E
Figure 4.8:
Connection of a TFT Panel with 1 Pixel per FPSCLK Period
panel power
control circuitry
1 pixel/clock
TFT
Figure 4.9:
Connection of a TFT Panel with 2 Pixels per FPSCLK Period
panel power
control circuitry
TFT Panel
2 pixels/clock
12/18
12/18
LVDS (Low Voltage Differential Signaling) interface is also supported. The module can accept
direct connection of LVDS or PanelLink devices with transmitter/receiver chips. For example,
LVDS support is provided by National Semiconductor DS90C383/4 (3.3 V, 65 MHz) or Texas
Instruments SN75LVDS83/2 (3.3 V, 65 MHz) chips. Silicon Image SiI100 is a PanelLink chipset.
Panels with LVDS or PanelLink interfaces are connected via J21 header (AMP 5-147377-2,
counterpart
АМР
111196-2). Table 4.11 below shows pinout of J21 connector.
Figure 4.10 illustrates 24-bit interface for TFT LVDS panels. Figures 4.11 and 4.12 show samples
of 24-bit interfaces for TFT and DSTN PanelLink panels respectively.
Table 4.11:
LVDS Connector J21 Pinout
Pin #
Signal
Pin #
Signal
1
VDD_EN
11
TxOUT2_H
2
DISPEN
12
TxOUT2_L
3
TxOUT0_H
13
GND
4
TxOUT0_L
14
GND
5
GND
15
TxOUT3_H
6
GND
16
TxOUT3_L
7
TxOUT1_H
17
GND
8
TxOUT1_L
18
GND
9
GND
19
TxCLK_OUT_H
10
GND
20
TxCLK_OUT_L
Note:
DSTN LVDS panels are not supported.