Explore EP9134, Руководство пользователя

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User Guide — EP9134_UG V0.7
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Section 3 Detail Functional Descriptions
3.1 General
The chip provides an IIC (SCL3/SDA3) serial bus interface to communicate with the host. The IIC address
for this slave IIC interface is "0111_A2_A1_A0_x" (where x=1 for read and x=0 for write). A2, A1 and A0
are programmable by pins
3.2 IIC Interface
The IIC bus interface uses a Serial Data line (SDA at pin SDA3) and a Serial Clock Line (SCL at pin SCL3)
for data transfer. The chip acts as a slave for receiving and transmitting data over the serial interface. All
devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is
exercised on both lines with external pull-up resistors, the value of these resistors is system dependent.
When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external
pull-up resistors.
Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes
state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on
SDA must change only when SCL is LOW.
The standard IIC traffic protocol is illustrated in the following Figure:
Figure 3-1 IIC Bus Transmission Protocol
SCL
SDA
Start
Signal
Ack
Bit
1 2 3 4 5 6 7 8
MSB LSB
1 2 3 4 5 6 7 8
MSB LSB
Stop
Signal
No
SCL
SDA
1 2 3 4 5 6 7 8
MSB LSB
1 2 5 6 7 8
MSB LSB
Repeated
3 4
9 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address Read/ Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
9 9
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write
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