X
X
R
R
P
P
7
7
7
7
2
2
0
0
/
/
7
7
7
7
2
2
4
4
/
/
7
7
7
7
2
2
5
5
E
E
V
V
B
B
-
-
D
D
E
E
M
M
O
O
-
-
1
1
Q
Q
u
u
a
a
d
d
C
C
h
h
a
a
n
n
n
n
e
e
l
l
D
D
i
i
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
/
/
P
P
F
F
M
M
D
D
e
e
m
m
o
o
B
B
o
o
a
a
r
r
d
d
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
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P
P
o
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w
w
e
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r
r
M
M
a
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n
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a
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g
g
e
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m
m
e
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n
n
t
t
S
S
y
y
s
s
t
t
e
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m
m
© 2014 Exar Corporation
4/16
Rev. 2.0.0
Name
Pin Number
Description
GL_RTN1-4
39,33, 28,22 Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
GL1-GL4
38,32, 27,21 Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
GH1-GH4
36,30, 25,19 Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
LX1-LX4
37,31, 26,20
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching
node at the junction between the two external power MOSFETs and the inductor. These
pins are also used to measure voltage drop across bottom MOSFETs in order to provide
output current information to the control engine.
BST1-BST4
35,29, 24,18
High side driver supply pin(s). Connect BST to the external capacitor as shown in the
Typical Application Circuit on page 5. The high side driver is connected between the
BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each
cycle.
GPI0-GPIO1
9,10
These pins can be configured as inputs or outputs to implement custom flags, power
good signals, enable/disable controls and synchronization to an external clock.
PSIO0-PSIO2
13,14,15
Open drain, these pins can be used to control external power MOSFETs to switch loads
on and off, shedding the load for fine grained power management. They can also be
configures as standard logic outputs or inputs just as any of the GPIOs can be
configured, but as open drains require an external pull-up when configured as outputs.
SDA, SCL
11,12
SMBus/I
2
C serial interface communication pins. These pins can be configured open
drain or pseudo-TTL requiring a pull-up resistor.
VOUT1-VOUT4
5,6,7,8
Connect to the output of the corresponding power stage. The output is sampled at least
once every switching cycle
LDO5
44
Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of
the IC is in the stand-by mode. This LDO is also used to power the internal Analog
Blocks.
ENABLE
40
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,
registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be
placed into shutdown. Active channels will automatically be ramped down, if desired,
prior to the disabling of the chip.
DGND
17
Digital ground pin. This is the logic ground connection, and should be connected to the
ground plane close to the PAD.
NC
1,3,42
No Connect
