X
X
R
R
P
P
7
7
7
7
2
2
0
0
/
/
7
7
7
7
2
2
4
4
/
/
7
7
7
7
2
2
5
5
E
E
V
V
B
B
-
-
D
D
E
E
M
M
O
O
-
-
1
1
Q
Q
u
u
a
a
d
d
C
C
h
h
a
a
n
n
n
n
e
e
l
l
D
D
i
i
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
/
/
P
P
F
F
M
M
D
D
e
e
m
m
o
o
B
B
o
o
a
a
r
r
d
d
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
e
P
P
o
o
w
w
e
e
r
r
M
M
a
a
n
n
a
a
g
g
e
e
m
m
e
e
n
n
t
t
S
S
y
y
s
s
t
t
e
e
m
m
© 2014 Exar Corporation
3/16
Rev. 2.0.0
XRP7720-DEV PIN ASSIGNMENT
33
32
31
30
29
28
27
26
24
25
20
19
17
18
16
15
13
14
12
10
1
2
3
4
5
6
7
8
9
36
37
39
38
40
41
43
42
44
21
35
NC
AGND
NC
AVDD
VOUT1
VOUT2
VOUT4
GPIO0
GPIO1
GL2
LX2
GH2
BST2
GL_RTN3
GL3
LX3
GH3
BST3
VCCD3-4
SCL
PSIO
1
PSIO
2
DVDD
PSIO
0
DGND
BST
4
GH
4
LX
4
GL
4
LDO
5
5VEXT
NC
VCC
ENABLE
GL
1
LX
1
GH
1
BST
1
VCCD
1-2
VOUT3
Exposed Pad: AGND
XRP7720-DEV
TQFN
7mm X 7mm
11
SDA
23
GL_RTN2
34
GL
_RTN
1
22
GL
_RTN
4
Figure 2: XRP7720-DEV Pin Assignment
XRP7720-DEV PIN DESCRIPTION
Name
Pin Number
Description
VCC
41
Input voltage. Place a decoupling capacitor close to the pin. This input is used in UVLO
fault generation.
DVDD
16
1.8V supply for digital circuitry. Connect pin to AVDD. Place a decoupling capacitor
close to the pin.
VCCD1-2
VCCD3-4
23,34
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail(for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible etch.
AGND
2
Analog ground pin. This is the small signal ground connection.
