EVGA nForce 3 250, Руководство пользователя

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Figure 3.4
Advanced Chipset Features
The Advanced Chipset Features setup option is used to change the
values of the chipset registers. These registers control most of the
system options in the computer. See Figure 3.4 below.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Set this function to one of
the configuration options:
Auto, 2.0, 2.5 or 3.0 . Unless the CAS Latency
is known, Auto should be selected.
SDRAM RAS-to-CAS Delay
This field allows for a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Set this
function to one of the configuration options:
Auto, 2, 3, 4, 5, 6 or 7 . The
Default setting for this function is Auto .
SDRAM Cycle Time
The Default and recommended setting for this function is Auto . System
performance can be improved if adjusted; however, system instability
may occur if this setting is not set to the proper value.
SDRAM RAS Precharge Time
If an insufficient number of cycles are allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. If this item is set to a
smaller increment, the system yields faster performance; however, if the
item is set to a larger number, the system yields more stable
performance. This field applies only when synchronous DRAM is
installed in the system. Set this function to one of the configuration
options:
Auto, 2, 3, 4, 5 or 6 . The Default setting for this function is Auto .
1T/2T Memory Timing
This feature sets the memory timing for the system. Set this function to
one of the configuration options:
Auto, 1T and 2T .