Eurotech CPU-1450, Руководство пользователя, Страница: 25 / 43

Chapter 5 Soft Power Management Registers
The SPM register model consists of a number of fixed register blocks that perform designated functions. A
register block consists of a number of registers that perform Status, Enable and Control Functions.
Status bits are only set through some defined hardware events.
Unless otherwise noted, Status bits are cleared by writing a HIGH to that bit position, and upon VTR
POR. Writing 0 has no effect.
Status bits only generate interrupts while their associated bit in the enable register is set.
Function bit positions in the status register have the same bit position in the enable register.
Wake-up event configuration is retained by the battery backup power.
For a first approach to power management it is not required to know all the registers involved.
The program examples in the next chapter set the power mode as required for a quick test of power
management.
As a reference, for a more detailed approach, the following pages show a list of interesting registers used in
the code examples.