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About This Document

The guidelines outline recommended design practices when developing standalone or add-on systems based on

the ESP32-C3 series of products, including ESP32-C3 SoCs, ESP32-C3 modules and ESP32-C3 development

boards.

Document Updates

Please always refer to the latest version on

https://www.espressif.com/en/support/download/documents

.

Revision History

For the revision history of this document, please refer to the

last page

.

Documentation Change Notification

Espressif provides email notifications to keep you updated on changes to technical documentation. Please

subscribe at

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. Note that you need to update your subscription to receive

notifications of new products you are not currently subscribed to.

Certification

Download certificates for Espressif products from

www.espressif.com/en/certificates

.

Содержание ESP32-C3 Series

Страница 1: ...ESP32 C3 Family Hardware Design Guidelines Version 1 0 Espressif Systems Copyright 2021 www espressif com...

Страница 2: ...support download documents Revision History For the revision history of this document please refer to the last page Documentation Change Notification Espressif provides email notifications to keep you...

Страница 3: ...ical Layout Problems and Solutions 24 3 8 1 Ripple in the power supply is not large but the RF transmit TX performance is rather poor 24 3 8 2 Ripple in power supply is small during packet transmissio...

Страница 4: ...Family PCB Layout 16 12 Placement of ESP32 C3 Modules on Base Board Antenna Feed Point on the Right 17 13 Placement of ESP32 C3 Modules on Base Board Antenna Feed Point on the Left 17 14 Keepout Zone...

Страница 5: ...C3 family provides a highly integrated way to implement Wi Fi and Bluetooth LE technologies using a complete RF subsystem including a antenna switch RF balun power amplifier low noise amplifier LNA fi...

Страница 6: ...0 21 SPICLK 22 SPID 23 SPIQ 24 U0RXD 27 U0TXD 28 XTAL_N 29 XTAL_P 30 GND 33 VDDA 32 VDDA 31 GPIO19 26 GPIO18 25 U1 40MHz 10ppm XIN 1 GND 2 XOUT 3 GND 4 5 4 3 2 1 B A The values of C8 L2 and C9 vary wi...

Страница 7: ...2 6 CHIP_EN 7 MTMS 9 MTDI 10 VDD3P3_RTC 11 MTCK 12 MTDO 13 GPIO8 14 GPIO9 15 GPIO10 16 VDD3P3_CPU 17 VDD_SPI 18 SPIHD 19 SPIWP 20 SPICS0 21 SPICLK 22 SPID 23 SPIQ 24 U0RXD 27 U0TXD 28 XTAL_N 29 XTAL_P...

Страница 8: ...SP32 C3 XTAL_32K_N GPIO2 6 CHIP_EN 7 MTMS 9 MTDI 10 VDD3P3_RTC 11 MTCK 12 MTDO 13 GPIO8 14 GPIO9 15 GPIO10 16 VDD3P3_CPU VDD_SPI SPIHD SPIWP GPIO3 8 Figure 3 ESP32 C3 Family Analog Power Supply Pins N...

Страница 9: ...ng of the power supply and the power up and reset sequence timing of the chip 2 2 2 Reset CHIP_EN can be used as the reset pin of ESP32 C3 family When CHIP_EN is at low level the reset voltage VIL_nRS...

Страница 10: ...trace to reduce the drive capability of the crystal and to minimize the impact of crystal harmonics on RF performance The value of this component initially of 24 nH depends on further testing Note tha...

Страница 11: ...deviation of more than 10 ppm unstable performance over operating temperature range etc may lead to the malfunction of ESP32 C3 family resulting in RF performance degradation 2 4 2 RTC Clock optional...

Страница 12: ...s in the matching network are subject to the actual antenna and PCB layout 2 6 UART You need to connect a 499 resistor to the U0TXD line to suppress the 80 MHz harmonics 2 7 ADC It is recommended to a...

Страница 13: ...apping Pins Booting Mode 1 Pin Default SPI Boot Download Boot GPIO2 N A 1 1 GPIO8 N A Don t care 1 GPIO9 Internal pull up 1 0 Enabling Disabling ROM Code Print During Booting Pin Default Functionality...

Страница 14: ...r Input GPIOs can also be set to generate edge triggered or level triggered CPU interrupts All digital IO pins are bi directional non inverting and tristate including input and output buffers with tri...

Страница 15: ...pedance state IE 0 1 input enabled in high impedance state IE 1 2 input enabled pull down resistor enabled IE 1 WPD 1 3 input enabled pull up resistor enabled IE 1 WPU 1 4 output enabled pull up resis...

Страница 16: ...details in Table 5 Table 5 Power Up Glitches on Pins Typical Time Period Pin Glitch1 ns MTCK Low level glitch 5 MTDO Low level glitch 5 GPIO10 Low level glitch 5 U0RXD Low level glitch 5 GPIO18 Pull u...

Страница 17: ...provided that there is a complete GND plane under the RF module and crystal The fourth layer is the BOTTOM layer where power traces are routed It is not recommended to place any components on this la...

Страница 18: ...point of the antenna should be closest to the board as shown in Figure 13 and Figure 12 1 2 3 4 5 Base board Figure 12 Placement of ESP32 C3 Modules on Base Board Antenna Feed Point on the Right 1 2 3...

Страница 19: ...t the module is not covered by any metal shell Besides the antenna area of the module and the area 15 mm outside the antenna should be kept clean namely no copper routing components on it as shown in...

Страница 20: ...acitor Then the power traces are divided into two ways from here and form a star shape topology thus reducing the coupling between different power pins Note that all decoupling capacitors should be pl...

Страница 21: ...urround the crystal traces with ground copper on all sides and dense ground vias for better isolation There should be no via for the clock input and output traces which means the traces cannot cross l...

Страница 22: ...d have 50 single ended characteristic impedance The reference plane is the second layer A type matching circuit should be reserved on the RF trace and placed close to the chip The RF trace should have...

Страница 23: ...only to parallel capacitors near the chip The trace highlighted in Figure 16 is the stub Figure 19 ESP32 C3 RF Stub in a Four layer PCB Design The ground plane on the adjacent layer needs to be comple...

Страница 24: ...2 C3 Family PCB Stack up Design 3 6 Flash Place the reserved serial resistor on the SPI interface close to the chip side Route the SPI traces on the inner layer e g the third layer whenever possible A...

Страница 25: ...m a cross layer design High frequency signal traces under the crystal such as UART trace Inductive or radiation components around the crystal such as inductors and entennas Solution This problem is ca...

Страница 26: ...en designing PCB layout Solution Keep the antenna away from crystals Do not route high frequency signal traces close to the RF trace For details please see Section 3 Espressif Systems 25 Submit Docume...

Страница 27: ...dule s flash If you need to download your own firmware please follow the steps below 1 Set the module to UART Download mode by pulling IO9 pulled up by default low and IO2 high 2 Power on the module a...

Страница 28: ...ry Revision History Date Version Release notes 2021 05 28 V1 0 Official release 2021 04 09 V0 5 Preliminary release Espressif Systems 27 Submit Documentation Feedback ESP32 C3 Family Hardware Design G...

Страница 29: ...ing Guide Espressif Product Ordering Information Certificates Notification Subscription Sales and Technical Support Sales Questions Technical Inquiries Get Samples Developer Zone ESP32 Forum GitHub Co...

Страница 30: ...OPOSAL SPECIFICATION OR SAMPLE All liability including liability for infringement of any proprietary rights relating to use of information in this document is disclaimed No licenses express or implied...

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